I have a customer that wants to know how do they determine where the actual flash data begins after the header.
Years ago they wrote code to use a processor to write .jic files into serial flash devices. They are looking to do the same thing in their current design. The problem they are running into is that the header of the file generated by 18.1 (for an Arria 10) appears to be 1 byte smaller than the header generated by 13.1 (for a Cyclone V) -> 161 bytes vs 162 bytes.
Their question is how do they know where the FPGA image data starts?
I'm Steve's customer. Attached is an image of my .jic file. I found a mistake in my .jic file generation. This is the corrected file and I now believe the header is 163 or 164 bytes. Can somebody tell me based on this image where the FLASH data begins? I thought that it was the first FF but this does not seem to be the case. I have tried to set up the file generation options to match the design done in 13.1.
As another data point, it appears that the FPGA is reading in the file but rejecting it based on some error in the file.
You can generate a .rpd file (binary file) which only contains the configuration data ( this will exclude the header from .jic file). If you are using your own processor to write the EPCQ device, then you should be using the .rpd file that contains the AS configuration bitstream. The .jic file can only be use correctly by the Quartus programmer when writing into the EPCQ/EPCS flash devices. You can refer to the following link on the steps to generate the .rpd file:
Thanks for the help. I created the .rpd file and the FPGA still fails to load. We tried it in both little endian and big endian. We are using a Micron MT25QU256 and we followed the instructions in Bug ID 543053 about using the MT25Q devices. Is there any additional information available about using these devices that may help us debug the problem?
I know this is a very old thread but for the record.
You have to set the Non-Volatile Status Register on MT25Q manually with your ROM writer.
Address mode selection: Must be 4-Byte address mode
Reset/Hold disable : Must be Disabled
Dummy clock cycles : Must be 4
.rdp file needs to be bit swapped, if you was trying to flash it with a ROM writer.
If you were using .jic file and doing JTAG-Indirectly programming, it will configure Non-Volatile Status Register for you automatically.
You mentioned this Bug ID 543053, are you referring to this KDB information?
Did your processor set the correct NVCR value into the MT25QU flash device before writing the .rpd file? As explained in Bug ID 543053, the MT25QU have a non-volatile configuration register (NVCR). The NVCR must be set to an appropriate value according to the MT25Q device and configuration mode in FPGA device families. For Arria 10 the dummy clock cycles is 10 and require to use 4 byte addressing mode.
The default generated .rpd file from Quartus tools is little endian format. By default the programming the .jic/pof file, the Quartus programmer will perform the bit swapping (LSb first) before writing the data into the EPCS/EPCQ/EPCQA device. Thus you need to perform the bit swapping when using the little endian .rpd file before writing the data into MT25QU device. If you set the big endian option in the Convert Programming File tools when generating the .rpd file, then you don’t require to perform the bit swapping since the generated .rpd file is in big endian format.