Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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JTAG pins constraints (18.1)

RZhen11
New Contributor I
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I have a project once had no constraint warning. Then I enabled dynamic reconfiguration ports for Transceiver toolkit.

Since then, every compile show unconstrained warning for:

altera_reserved_ntrst

altera_reserved_tdi

altera_reserved_tms

altera_reserved_tdo

 

Indeed, I have not specified anywhere about these pins. Similar source code in previous revisions when there is no such warnings.

In a newly created project, I have the same Unconstrained Paths warnings.

I am curious, do I have to constraint JTAG pins? 

 

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