LVDS_DIRECT_LOOPBACK_MODE - need more detail on what "adjacent pair" means

[Altera_Forum]

I am looking into using the setting LVDS_DIRECT_LOOPBACK_MODE for a current design project but I am confused by this sentence in the description: "When this feature is enabled, data coming in from the adjacent RX pair gets looped back to the TX pair." What constitutes "adjacent"? The device I am currently working with is a Cyclone V GX - 5CGXFC5C6F27C7 to be exact.  

 -Mark

[Altera_Forum]

Nevermind. Looks like this does not apply to Cyclone devices (from ON-LINE MANUAL): 

 A logic option that enables the LVDS direct loopback mode on a true differential output pin.  You must assign this option from an input pin to an output pin and you should assign both pins true differential I/O standards. When this option is turned on, data coming in from the adjacent RX pin pair gets looped back to the TX pin pair.  This option is useful for verifying the TX and RX buffers by checking the data transmitted and received.  This option is ignored if it is applied to anything other than a pin or a top-level design entity. This option is available only for Stratix V devices.

[Altera_Forum]

Hi, 

 You are right, the loopback mode is used for true differential LVDS pins debugging. By looping data directly from RX to TX, this can help to check if the bit error observed in the FPGA is actually due to incoming signal issue from the other source.