LVDS IO error

[mode]

Hi, again

I try very simple case as attached.

But It is same error result.

Please advice how to interface lvds IO input by primitives

Thanks

[SreekumarR_G_Intel]

Hello,

Can you give me the device part number ? Did you check the clk1(n) is connected to the clk_n pin of the device ?

Thank you ,

Regards,

Sree

[mode]

FPGA Part number is EP4CE15F17C8N (Cyclone iV)

However i find the reason that is naming of negative pin.

Whenever define one of differential pin, tool generate name(n) automatically.

After that i annotate back it to Design PIN.

This is error happen.

Can you teach me how to process differential PIN define correctly?

Thanks

David

[SreekumarR_G_Intel]

There are many ways you can do ; usually way i do is assign the signal I/O standard as "LVDS " and assign the xxx_p pin in the pin planner or assignment editor or qsf assignment, then xxx_n will automatically assign by the tool .

Hope helps ;

Thank you,

Regards,

Sree