LVDS Interface and PCB layout requirments

[CSegu]

Dear Sir,

I am using ALTERA LVDS_TX and LVDS_RX IPs to implement LVDS communication in loopback on a custom developed FPGA board. I have developed the firmware and runs on the CYCLONE V GX starter kit as shown in attached timing diagram "Working.png". But when running the same firmware on my custom board the output is always "00". I have checked continuity of traces with the meter and no open or short connections found between FPGA and LVDS connector. Attached is my schematic diagram for LVDS interface using BANK8A with VCCIO 2.5V. I have also added termination 100 ohm resistor later manually across LVDS RX lines but no success. Do I need to use external resistors for Cyclone V GX LVDS transmitter lines or are these available internally? On the Cyclone V GX starter kit these are not used. There is just direct line connections between LVDSTX+/TX- and LVDS +rx/rx-. Note that LVDS TX/RX lines are synchronized with clock.

For what reasons could the LVDs RX Inputs are always "00" on custom design board. What other additional checks do you recommend? Is there possibility of having the internal FPGA PLL or LVDS drivers faulty ? Do you have any clear guidelines of how to set up LVDS TX and LVDS RX PCB layout interface on a FR4 PCB for Cyclone V GX  5CGXFC5C6F27C6 device?

Thank you.

Regards,

[AnandRaj_S_Intel]

Hi,

If design is working on Dev Kit, then board need to be checked.

since we are not seeing the rx_clk, we can suspect that pll from board design point of view.

1. Check RREF_TL, If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND.
2. Also check VCCA_FPLL
3. VCCH_GXBL and VCCA_FPLL must always be powered up for the PLL operation.

Try to create a simple pll design and see if we are getting expected output to eliminate the above doubt.

For LVDS PCB layout requirements refer below links

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp_lvdsboard.pdf

https://www.intel.com/content/dam/altera-www/global/en_US/others/download/board-layout-test/Altera_Device_Layout_Review_Worksheet.doc

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand

[CSegu]

Dear ARS, Attached are the schematic diagrams. As shown VCCA_FPLL, VCCH_GXBL and VCCA_FPLL are all connected to power supply 2.5V. RREF_TL was not connected. To clarify is it only the RREF_TL pin that requires a 2.0-kΩ +/- 1% to GND? Is this the root cause of such problem? Do we need this resistor for LVDS SERDES also or just high speed GXB transceivers ? Do the VREFB5 of every bank require such resistor? Thank you. Regards, Clive

[CSegu]

Hi Anad, Is the RREF_TL pin avaialble on pin B1 only of the ? I couldn`t find it anywhere else in 5CGXFC5C6F27C7N device. Is this requird for LVDS SERDES and REFCLK input pins also ? Thanks. Regards, Clive Seguna

[AnandRaj_S_Intel]

Hi Clive,

1. Yes, B1 is the pin RREF_TL for ​Device 5CGXFC5C6F27C7N.
2. Since we are using SERDES which uses a PLL.. we have to connect  RREF_TL pin on that side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND.

Above guideline is valid If any PLL, REFCLK pin, or transceiver channel is used.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand