LVDS timing issue in cyclone v device

[Altera_Forum]

Hello, 

 I have got some problems to implement two copies of the same interface into a cyclone v device.   - Each interface is edge-aligned and the lvds data and lvds clock are mapped on the same bank.  - The clock speed is at 200 MHz and the data is sampled as DDR. - For implementation i used the ALTLVDS_RX ip-core. In the documentation "Cyclone V Device Handbook Volumne 1, Receiver Blocks in Cyclone V Devices" it is mentioned that, with a DDR interface and a serialization factor of 2, the ip-core will bypass any deserializer functionality.  - That means in my case that he will include, by using this core, automaticaly the altddio ip-core and therefore i need a pll (integer, clock synchronous) with a 90° phase shift. - Each interface got his own clock domain, there is no clock domain crossing, the data is written into mlab blocks.  So my problem is, that with the identically constraining of the inputs, i got a setup slack of - 2.0 ns at the inputs of the altddios. The other interface is without any timing isues. Is there any mistake in my implementation and, if not, are there any options?  I really appreciate any help

[Altera_Forum]

Here the related information 

 +----------------------------------------------------------------- ; Data Arrival Path  +---------+---------+----+------+--------+------------------------ ; Total ; Incr ; RF ; Type ; Fanout ; Location  +---------+---------+----+------+--------+------------------------ ; 2.500 ; 2.500 ; ; ; ;  ; 2.500 ; 0.000 ; ; ; ;  ; 2.500 ; 0.000 ; F ; ; ;  ; 2.600 ; 0.100 ; F ; iExt ; 1 ; PIN_B6  ; 8.923 ; 6.323 ; ; ; ;  ; 2.600 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X14_Y81_N1  ; 3.590 ; 0.990 ; FF ; CELL ; 1 ; IOIBUF_X14_Y81_N1  ; 3.590 ; 0.000 ; FF ; IC ; 2 ; DDIOINCELL_X14_Y81_N14  ; 8.923 ; 5.333 ; FF ; CELL ; 0 ; DDIOINCELL_X14_Y81_N14  +---------+---------+----+------+--------+------------------------  +---------------------------------------------------------------------- ; Data Required Path  +---------+----------+----+------+--------+---------------------------- ; Total ; Incr ; RF ; Type ; Fanout ; Location  +---------+----------+----+------+--------+---------------------------- ; 3.750 ; 3.750 ; ; ; ;  ; 7.418 ; 3.668 ; ; ; ;  ; 3.750 ; 0.000 ; ; ; ;  ; 3.750 ; 0.000 ; ; ; 1 ; PIN_H15  ; 3.750 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X40_Y81_N1  ; 4.690 ; 0.940 ; RR ; CELL ; 1 ; IOIBUF_X40_Y81_N1  ; 6.225 ; 1.535 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y62_N0  ; 6.533 ; 0.308 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y62_N0  ; 6.533 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y56_N0  ; 2.390 ; -4.143 ; RR ; COMP ; 1 ; FRACTIONALPLL_X0_Y56_N0  ; 2.390 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y60_N1  ; 3.856 ; 1.466 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y60_N1  ; 4.139 ; 0.283 ; FF ; IC ; 1 ; CLKCTRL_G0  ; 4.448 ; 0.309 ; FF ; CELL ; 792 ; CLKCTRL_G0  ; 6.941 ; 2.493 ; FF ; IC ; 3 ; DDIOINCELL_X14_Y81_N14  ; 7.418 ; 0.477 ; FR ; CELL ; 0 ; DDIOINCELL_X14_Y81_N14  ; 7.308 ; -0.110 ; ; ; ;  ; 7.308 ; 0.000 ; ; uTsu ; 0 ; DDIOINCELL_X14_Y81_N14  +---------+----------+----+------+--------+----------------------------  1.) Why the fitter is implement that huge amount of delay to the ddio ? 2.) Is this just a report bug or is he using the fractional pll ?