Hi everyone,I have tried to implement a LVDS_TX IP Core on an Arria 10 FPGA using a external IOPLL to drive its clocks, but for some reason I keep getting timing errors at the internal registers of the LVDS_TX core. Those errors do not come up on an equivalent implementation using an internal IOPLL (i.e a IOPLL embedded on the own LVDS_TX), and cannot figure out why. Could someone help me out with this? I have been working on this for a few days and I'm running out of ideas... To ease things I have attached an ultrasimple design that exemplifies the problem: it just contains a 1-bit LVDS_TX with a serialization factor of 4, and an external IOPLL connected to it. The IOPLL generates the fast lvds clock (1GHz, 180º, 50% Duty Cycle), the loaden signal (250MHz, 270º, 25% DC) and the core or parallel clock (250MHz, 0º, 50% DC) from a 100MHz input clock, just as stated in the LVDS IP documentation. The input clock is declared on a SDC file and the rest of the clocks are derived by means of derive_pll_clocks. Here is the design: http://www.alteraforum.com/forum/attachment.php?attachmentid=13107&stc=1 And the SDC file's contents:
create_clock -name CLK_JAJA -period 10.000 derive_pll_clocks derive_clock_uncertaintyThe IOPLL was generated in LVDS compensation mode, and the "Enable LVDS_CLK/LOADEN 0" option selected, as indicated in the documentation of the LVDS IP. When I compile this design (you can try yourself if you don't believe it :)) timequest shows setup violations from all the tx.tx_reg[x] registers within the core (driven by the parallel clock) to the corresponding tx_internal_reg latches (driven by the lvds fast clock). However, if I compile an equivalent LVDS_TX with an internal IOPLL, everything is just fine, no timing violations... I have compared the reports on both designs (internal and external IOPLLs) and verified that PLLs have the same output configurations; the only difference I see boils down to a property called "LVDS Delay Chain Setting" in the Fitter report\Resource Section\PLL Usage Summary. In the case of an internal PLL, this property is set to 12 for some reason, and in the case of an external PLL is set to zero, just because why not. http://www.alteraforum.com/forum/attachment.php?attachmentid=13108&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=13109&stc=1 I have also compared the data and clock paths in Timequest and apparently everything is the same excepting for the delays the IOPLL applies. There is an "unofficial" design example (http://www.alterawiki.com/wiki/lvds) of an LVDS_TX and an external IOPLL on a thread of the Altera Wiki, but the same timing issues appear after compilation. Is it me or Quartus just doesn't want to implement the external IOPLL as it should be done? Thanks in advance!