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Hi,
There is something I don't understand during the design compilation.
After the compilation, I have the following warning message :
Warning (332060): Node: rst was determined to be a clock but was found without an associated clock assignment.
Info (13166): Latch i2c_slave:i2c_slave_inst|sda_f~1 is being clocked by rst
This surprised me, so i watched in Technology Map Viewer this latch :
This is the sda_f~1 latch internal logic :
I don't see any clocked latch or flip flop, so I really don't understand this warning.
I don't want to assign to "rst" a clock assignment.
Does anyone know the reason of this warning ?
Thanks in advance,
Regards,
Antoine
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There must be an error in your HDL code that is making the compiler think this is a clock signal. Can you post the code?
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I think the problem is poor code or an error in the code. From what you posted:
process(sda_clk, start_async_rst)
begin
if (start_async_rst = '1') then
sda_f <= sda_in;
elsif (rising_edge(sda_clk)) then
sda_f <= sda_in;
end if;
end process;
sda_f is getting inferred as a latch instead of a register because the reset is coded incorrectly. sda_f should get 0, I would presume, when start_async_rst equals 1. As such, start_async_rst (and its source, rst) are inferred as a clock gate essentially, so Quartus thinks it needs a clock assignment. So I don't know if that is an error in the IP you got, but a coding issue is causing the warning.
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Ok, i see what is the problem.
I don't need an asynchronous reset, so i just rewrite it like this, and it works well :
process(sda_clk)
begin
if (rising_edge(sda_clk)) then
sda_f <= sda_in;
end if;
end process;
Thank you for your help,
Antoine
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Hi Antoine,
You might have to take a look at below link for cause and action of the "Node: <Node name> was determined to be a clock but was found without an associated clock assignment"
Regards,
Syafieq

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