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aroturier
Beginner
214 Views

Latch clocked by "rst" signal

Hi,

There is something I don't understand during the design compilation.

After the compilation, I have the following warning message :

Warning (332060): Node: rst was determined to be a clock but was found without an associated clock assignment.
Info (13166): Latch i2c_slave:i2c_slave_inst|sda_f~1 is being clocked by rst

This surprised me, so i watched in Technology Map Viewer this latch :

aroturier_1-1602513836123.png

This is the sda_f~1 latch internal logic :

aroturier_2-1602513913389.png

I don't see any clocked latch or flip flop, so I really don't understand this warning.

I don't want to assign to "rst" a clock assignment.

Does anyone know the reason of this warning ?

Thanks in advance,

Regards,

Antoine

 

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5 Replies
sstrell
Honored Contributor II
210 Views

There must be an error in your HDL code that is making the compiler think this is a clock signal.  Can you post the code?

aroturier
Beginner
191 Views

Hi @sstrell 

Tanks for your answer.

It is not my VHDL code, it is an IP form Lattice.

 

sstrell
Honored Contributor II
180 Views

I think the problem is poor code or an error in the code.  From what you posted:

process(sda_clk, start_async_rst)

begin
if (start_async_rst = '1') then
sda_f <= sda_in;
elsif (rising_edge(sda_clk)) then
sda_f <= sda_in;
end if;
end process;

sda_f is getting inferred as a latch instead of a register because the reset is coded incorrectly.  sda_f should get 0, I would presume, when start_async_rst equals 1.  As such, start_async_rst (and its source, rst) are inferred as a clock gate essentially, so Quartus thinks it needs a clock assignment.  So I don't know if that is an error in the IP you got, but a coding issue is causing the warning.

aroturier
Beginner
172 Views

Ok, i see what is the problem.

I don't need an asynchronous reset, so i just rewrite it like this, and it works well :

process(sda_clk)

begin
if (rising_edge(sda_clk)) then
sda_f <= sda_in;
end if;
end process;

 

Thank you for your help,

Antoine

SyafieqS_Intel
Moderator
199 Views

Hi Antoine, 


You might have to take a look at below link for cause and action of the "Node: <Node name> was determined to be a clock but was found without an associated clock assignment"

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/msgs/msgs/wsta_...


Regards,

Syafieq 


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