I am trying to get my head around the Altera Verification IP. The document that describes the subject is the "Avalon Verification IP Suite" user guide. This document contains description of a lot of functions but it falls short of explaining how everything connects together to actually make us carry out verification in a real teste bench. There is no document in existence anywhere that describes this process and no YouTube tutorial yet on this subject as well!
The closest that one can get to example is a rather highly cryptic testbench that can be downloaded in the form of ug_avalon_verification.zip file.
The examples provided for Avalon-MM component contain a package called test_template_pkg.vhdtemp along with a test program called test_template.vhdtemp and finally the testbench that instantiates the dut and test program components called tb.vhd. There are a few examples with code presented in VHDL and also Verilog.
The examples provided for Avalon-ST component are only in SystemVerilog and even more difficult to follow.
I want to ask Intel/Altera, why have you not provided more examples of how to use the VIP components? Also, why are the example of the Avalon-ST components even more obscure and in SystemVerilog only? Don't you think it is about time to create video tutorials on this subject or provide more examples on how to use them? The VIP components are quite complex and more guidance is required so the user is able to use them with confidence and not get intimidated.
Finally, what about examples of other Avalon interfaces? Also, what about the new BFMs like the ones used with AXI bus? Why do you not provide any examples for them? Do you not want a lot of people to use these at all?
This is old but mostly still relevant:
This is newer (not sure what's going on with the description there:
Nothing about simulating Avalon streaming, though.
It appears to me that the event_ functions are blocking calls. The signal_ are their counter parts that be used in a process to wait on i.e process will only execute when their is activity on the signal. The example code shows that the event_ functions are being used in the VHDL code while the signal_ functions are being used in the verilog code to do the exact same thing.
Are the examples inside the ug_avalon_verification.zip supposed to work? I am getting considerable difficulty trying to get it to compile and run.
The examples in the ug_avalon_verification do not work out of the box. I took quite a lot of effort to get them to work with my ActiveHDL by making changes to the scripts inside.
By the way, whenever there is an example project from Altera/Intel, the project itself is configured for Stratix or Arria device. Why is this done? Why not put a low end device in the project settings so the project can open on most people's computer without trouble? The same applies to Qsys files in example designs.