Linux Qsys Now "platform designer", from old time still has trouble never addressed.
ALT_PLL Altera FPGA IP open in a small window with scroll bar, if something is touched in this state after long time crash.
If enlarged scroll bar disappear and PLL can be edited but again doesn't save.
This trouble is present till version 15.0.
Tcl file is messed up and unreadable.
The only way to use PLL on linux platform is to import old PLL file then edit parameter by hand.
Attached actual file I patched to generate Frequency I need on my design.
When opened for edit all parameter are set in different unit and still try to save leave untouched.
How can I cure this unpleasant issue?
Linux Mint release 17.2
Intel I7, Sony Vaio Pro SVS1511C5E 16GB ram.
As oon picture crash.
When enlarged as shown just save if one clock output is selected (sometimes) again editing never succed and next open show new parameter not held.
After succesful add I try'd two times add 3 more clock for 200, 250 and 10MHz, changes never appear on .qsys file.
Project is shareable just removing two IP core.
I'm not sure why the old Megawizard is showing up in a new version of Quartus. I'd recommend simply deleting the PLL component from your system design and re-adding it.
Hi Sstrell, this issue as I wrote is still present from revision 15.0 When I learned how to write My Ip core modules.
Also in a new design if I add ALT_PLL has same behavior. See this
Enlarge, edit parameter then finish
Finish result in not saved PLL
Step 3 add ALT_PLL, enlarge then two times finish button.
step 4, edit Alt_PLL, just configure clock input 50MHz, C0 to 100MHz, c1 10MHz as from step 2, finish finish and IP remain as is from step 3.
Delete add again same deterministic sequence. Alt_PLL_Reconfigure has same issue, other IP work like a charm.
This as I stated never changed from at almost revision 15.0, I had no previous revision installed,
Hi Rsee, I loaded the file you sent back, I argue is just same I sent you.
Please OPEN QSYS (Platform Designer) LINUX version and try modify PLL settings:
Input clock 50MHz not 100
C1 Clock need a multiplier 2
C2 clock need a divider 5 to output 10Mhz clock
C3 ex set to 200MHz require a multiplier 4.
DSave and reopen, check change are on file.
If you can setup on Linux, and send back, then and only then you tested issue.
Quartus installed on Ubuntu 18.02_4 doesn't work so I cannot test till now.... I open another issue soon.
Hi RSree, sorry for what I have to write:
Are you an FPGA designer and proficient on HDl languages, Platform designer usage?
Why I am asking this? I feel as you are VERY far from what happen, from how a PLL work and never checked reconfigure PLL clocks input and PLL section feedback counters.
Issue is about some TCL error I cannot address, Verilog VHDL is just the generated design hardware.
Openiing the design file by hand then set the PLL block, refresh design and then load with all clock, generate correct IP core. Platform designer provided interface DOESN'T WORK!!! INTERFACE, SOFTWARE ISSUE, not HDL generated file.
See snapshot, see what happen to saved PLL has just one clock C0 is on module, where set up C0, C1, C2, input frequency is not 100MHz default MUST BE 50MHz, Optput need be what I select and MORE THAN ONE I repeat REPEAT C0, C1, C2...
Software code messed up is graphic interface, if you open is stretched and if you touch something it crash after a while. Resizing doesn't crash but NEVER save chenges on QSYS file. File is quite messed up.
About dummy Master, this is another point I fear you are far from HDL design, is a very simple useless module to quiet warning and silence bus when no controller are there.
Is very simple to "add new" from left ip core selector one just by new component then import vhdl file.
This missing tcl file ( I can setup on project and send you) is not affecting the culprit of issue YOU CANNOT EDIT NOR APPLY AND SAVE CHANGES TO PLL PARAMETER!!!! THIS FROM 15.0!!
I totally understand what you are trying to say, and able to understand the dummy block . My intension only want to show you that the Qsys file is not generated successfully with the design that you send.
Again with Verilog, we had an issue on certain versions between Verilog and VHDL languages . So only to isolate the language issue I have suggested the above procedure.