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dickelbeck
Beginner
181 Views

Lite: 17.1 upgrade to 20.1, now ramstyle not working, getting logic, not M9K blocks, won't fit

This code was working on Lite 17.1, and not is not.  The compiler path is correct, the (*ramstyle*) is being seen.  I verified this by temporarily putting bad syntax before the troublesome line.

Vendor neutral approach to dual port ram:

------------------------


module simple_dual_port_ram #(
parameter addrwidth = 8,
parameter datawidth = 32,
parameter block_ram_type = ""
)
(
input rst_i,
input rd_clk_i,
input rd_en_i,
input [addrwidth-1:0] rd_addr_i,
output [datawidth-1:0] rd_data_o,

input wr_clk_i,
input wr_en_i,
input [addrwidth-1:0] wr_addr_i,
input [datawidth-1:0] wr_data_i
);

localparam memdepth = 2**addrwidth;

generate
`ifdef IS_QUARTUS
if( block_ram_type == "cyclone10_m9k" ) begin : gen
(* ramstyle = "M9K" *) reg [datawidth-1:0] mem[memdepth-1:0];
end
else begin
reg BUG; // reg [datawidth-1:0] mem[memdepth-1:0];
end
`else
// http://www.latticesemi.com/en/Support/AnswerDatabase/7/3/735
if( block_ram_type == "lattice_pmi" ) begin : gen
reg [datawidth-1:0] mem[memdepth-1:0] /* synthesis syn_ramstyle = "block_ram" */;
end
else begin : gen
reg [datawidth-1:0] mem[memdepth-1:0];
end
`endif
endgenerate


assign rd_data_o = gen.mem[rd_addr_i];


always @( posedge wr_clk_i )
if( wr_en_i ) begin
//$display( "wr[%d]=%x", wr_addr_i, wr_data_i );
gen.mem[wr_addr_i] <= wr_data_i;
end

endmodule

// save for later
// /* synthesis ramstyle = "M9K, no_rw_check" */;

 

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3 Replies
dickelbeck
Beginner
176 Views

17.1 compiles this and it fits, easily.  But during the compilation I see a message that I don't see with v. 20.1:

 

Warning (276020): Inferred RAM node "uart_wishbone:uart0|uart_core:uart|uart_send:transmitter|bram_fifo:tx_fifo|block_ram:fifo_ram|simple_dual_port_ram:dualp_ram|gen.mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.

 

I sure like the part where it says, "Inferred RAM node...

 

Do I have to go back to 17.1?

 

157 Views

You described a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that behave as RAM. Analysis & Synthesis then replaces the registers with a RAM node that will later infer an instance of the altsyncram megafunction to implement the functionality of the registers using the memory blocks in the target device.

For further information related to this error, you can refer to this link: 
https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/winfer_...

dickelbeck
Beginner
116 Views

I think the lite version was dumbed down maybe to incentivise people to upgrade to pro version of the software.  Or, I think there is a bug here.

 

I found it easiest just to stay with version 17.x which continues to handle this situation as I want.

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