I am trying to write my own LVDS receiver (I can not use the standard one).
4 lvds lines, frequency 74.25 MHz, deserialization factor 7.
ALTDDIO_IN_component : ALTDDIO_IN GENERIC MAP ( intended_device_family => "Cyclone V", invert_input_clocks => "OFF", lpm_hint => "UNUSED", lpm_type => "altddio_in", power_up_high => "OFF", width => 4 ) PORT MAP ( datain => Serial_Data, inclock => Signal_FastClock, dataout_h => Signal_Data_D ) ; PROCESS( Signal_FastClock ) BEGIN IF( RISING_EDGE( Signal_FastClock ) ) THEN Signal_Data_Q <= Signal_Data_D; FOR I IN 0 TO 3 LOOP Signal_ShiftData( I ) <= Signal_ShiftData( I )( 5 DOWNTO 0 ) & Signal_Data_Q( I ); END LOOP; END IF; END PROCESS;
Signal_ShiftData is ARRAY( 0 TO 3 ) OF STD_LOGIC_VECTOR( 6 DOWNTO 0 );
Signal_FastClock is 519.75MHz
How can I describe this path so that it is fitted correctly? dataout_h is ok
First of all, thank you so much for reaching us.
My name is Eliath and I'll help you with the issue.
Please, could you tell me if you had some problems using our LVDS? or why you couldn't use it?
I'll need to review your project to see what exactly is happening and try to help you so...
Could you please share it with me please?