Simple Edge detector doesn't work, just pipeline of signal doesn't work.
monitor of incoming signals, output signals, routed output signals to two pin:
On one is stuck at 0, on the other sample S@1....
-- Interrupt request acknowledge management on edge
SEQIRQ_IFC: process(SYS_CLK, ResetIn_n)
begin
if(RESetIn_n = '0') then
Local_IRQ_sampler <= (others => '0');
Seq_IRQREQ <= '0'; -- No IRQ
else
if rising_edge(SYS_CLK) then
-- clock edge
-- IRQ Edge sampling
Local_IRQ_sampler(1) <= Local_IRQ_sampler(0);
Local_IRQ_sampler(0) <= ETH_IRQREQ; -- (Sample) Ethernet RX end of UPD packet irq accepted irq request <-- Ethernet RX end of UPD packet irq request
-- Flag management
-- if Local_IRQ_sampler(1) = '0' and Local_IRQ_sampler(0) = '1' then
-- Seq_IRQREQ <= '1'; -- request IRQ
-- else --if Local_IRQ_sampler(1) = '0' and Local_IRQ_sampler(0) = '0' then
Seq_IRQREQ <= Local_IRQ_sampler(0); --'0';
-- end if;
-- clock edge
end if; -- clock edge
end if; -- Reset run
end process;
Changed to simple pipeline, still output is not correct.
On top trace signal from this module, bottom trace from outside of module, routed to LA.
Middle is the ETH_IRQREQ sampled on this module.
Seq_irqreq is the entity pin.
On top entity pin is routed to two different pin by simple direct assignment.
Same signal routed to a uController pin, that pin is stuck at one.
Logic and pin routed to LA is stuck at 0, seems quartus leave logic unconnected and signals assigned to default status.
Link Copied
Update:
Entity interface:
-- Interrupt
ETH_IRQREQ : in Std_Logic := '0'; -- Ethernet RX end of UPD packet irq request
ETH_IRQACK : out Std_Logic := '0'; -- Ethernet RX end of UPD packet irq accepted
ETH_Status_Register : in Std_logic_Vector(7 downto 0) := (others => '0'); -- Status of transmitter/receiver
SEQ_IRQREQ : out Std_Logic := '0'; -- Controller irq request
moved signal out of process to be mere combinatorial....
DMA_ACK <= Local_DMA_ACK;
ETH_SEND <= Local_ETHREG;
SEQ_IRQREQ <= ETH_IRQREQ; -- Controller irq request <-- Ethernet RX end of UPD packet irq request
-- Local_PWR_FLT <= (others => '0');
-- Local_MODECFG <= (others => '0');
-- RD/WR Status flags
SEQ_Debug(3 downto 0) <= Local_StatePrb; -- state counter
SEQ_Debug(4) <= Local_DMA_ACK;
-- SEQ_Debug(5) <= Local_DMA_IsRDing;
SEQ_Debug(6) <= SPI_WR_READY;
SEQ_Debug(7) <= SPI_RD_READY;
SEQ_Debug(5) <= ETH_IRQREQ;
-- SEQ_Debug(6) <= '0';
-- SEQ_Debug(7) <= '0';
--------------------------------------------------------------------------
-- Entity - Signal connection End ----------------------------------------
--------------------------------------------------------------------------Signals:
ETHIRQ on this module from debug signal. (Element 5 of vector)
ETH_IRQ on external generating module
SEQ_Irqreq outside this module.
Freezed project files to document this again fool issue.
LA pin is low, uController sample High, seems SEQ_IRQREQ disappeared from design and default signal take on place.
Edit:
Top module:
Entity:
-- --- STM IO ---------------------------------
TXDE1_ST : inout Std_Logic := 'Z'; -- Released to controller
RX1_ST : inout Std_Logic := 'Z'; -- Released to controller
TX1_ST : inout Std_Logic := 'Z'; -- Released to controller
TXDE2_ST : inout Std_Logic := 'Z'; -- Active serial to Perihery
RX2_ST : inout Std_Logic := 'Z'; -- Active serial to Perihery
TX2_ST : inout Std_Logic := 'Z'; -- Active serial to Perihery
JTAGEN : out Std_Logic; -- User free I/O
........
-- signals:
signal Local_irq_req : std_Logic := '0'; -- IRQ Request
connection:
Local_irq_req, is mapped to external module SEQ_IRQREQ interface.
TX1_ST <= Local_irq_req;
....
JTAGEN <= Local_irq_req; --Local_SPI_Debug_Port(20); --SPI_MOSI1; -- LA 3 Local_Debug_PortW(3)
