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RRomano001
New Contributor I
414 Views

MAX 10 foolished by? WHY???

Simple Edge detector doesn't work, just pipeline of signal doesn't work.

monitor of incoming signals, output signals, routed output signals to two pin:

On one is stuck at 0, on the other sample S@1....

-- Interrupt request acknowledge management on edge SEQIRQ_IFC: process(SYS_CLK, ResetIn_n) begin if(RESetIn_n = '0') then Local_IRQ_sampler <= (others => '0'); Seq_IRQREQ <= '0'; -- No IRQ else if rising_edge(SYS_CLK) then -- clock edge -- IRQ Edge sampling Local_IRQ_sampler(1) <= Local_IRQ_sampler(0); Local_IRQ_sampler(0) <= ETH_IRQREQ; -- (Sample) Ethernet RX end of UPD packet irq accepted irq request <-- Ethernet RX end of UPD packet irq request -- Flag management -- if Local_IRQ_sampler(1) = '0' and Local_IRQ_sampler(0) = '1' then -- Seq_IRQREQ <= '1'; -- request IRQ -- else --if Local_IRQ_sampler(1) = '0' and Local_IRQ_sampler(0) = '0' then Seq_IRQREQ <= Local_IRQ_sampler(0); --'0'; -- end if; -- clock edge end if; -- clock edge end if; -- Reset run end process;  

Changed to simple pipeline, still output is not correct.

On top trace signal from this module, bottom trace from outside of module, routed to LA.

Middle is the ETH_IRQREQ sampled on this module.

Seq_irqreq is the entity pin.

On top entity pin is routed to two different pin by simple direct assignment.

Same signal routed to a uController pin, that pin is stuck at one.

Logic and pin routed to LA is stuck at 0, seems quartus leave logic unconnected and signals assigned to default status.

timing.png

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7 Replies
RRomano001
New Contributor I
80 Views

 

 

Update:

 

Entity interface:

-- Interrupt ETH_IRQREQ : in Std_Logic := '0'; -- Ethernet RX end of UPD packet irq request ETH_IRQACK : out Std_Logic := '0'; -- Ethernet RX end of UPD packet irq accepted ETH_Status_Register : in Std_logic_Vector(7 downto 0) := (others => '0'); -- Status of transmitter/receiver   SEQ_IRQREQ : out Std_Logic := '0'; -- Controller irq request

 

 

moved signal out of process to be mere combinatorial....

DMA_ACK <= Local_DMA_ACK;   ETH_SEND <= Local_ETHREG;   SEQ_IRQREQ <= ETH_IRQREQ; -- Controller irq request <-- Ethernet RX end of UPD packet irq request     -- Local_PWR_FLT <= (others => '0'); -- Local_MODECFG <= (others => '0');   -- RD/WR Status flags   SEQ_Debug(3 downto 0) <= Local_StatePrb; -- state counter SEQ_Debug(4) <= Local_DMA_ACK; -- SEQ_Debug(5) <= Local_DMA_IsRDing; SEQ_Debug(6) <= SPI_WR_READY; SEQ_Debug(7) <= SPI_RD_READY; SEQ_Debug(5) <= ETH_IRQREQ; -- SEQ_Debug(6) <= '0'; -- SEQ_Debug(7) <= '0'; -------------------------------------------------------------------------- -- Entity - Signal connection End ---------------------------------------- --------------------------------------------------------------------------

Signals:

 

ETHIRQ on this module from debug signal. (Element 5 of vector)

 

ETH_IRQ on external generating module

 

SEQ_Irqreq outside this module.

 

Freezed project files to document this again fool issue.

LA pin is low, uController sample High, seems SEQ_IRQREQ disappeared from design and default signal take on place.

 

Screenshot from 2019-06-06 10:48:39.png

 

 

 

 

Edit:

Top module:

Entity:

-- --- STM IO --------------------------------- TXDE1_ST : inout Std_Logic := 'Z'; -- Released to controller RX1_ST : inout Std_Logic := 'Z'; -- Released to controller TX1_ST : inout Std_Logic := 'Z'; -- Released to controller TXDE2_ST : inout Std_Logic := 'Z'; -- Active serial to Perihery RX2_ST : inout Std_Logic := 'Z'; -- Active serial to Perihery TX2_ST : inout Std_Logic := 'Z'; -- Active serial to Perihery     JTAGEN : out Std_Logic; -- User free I/O   ........   -- signals: signal Local_irq_req : std_Logic := '0'; -- IRQ Request

 

 

connection:

Local_irq_req, is mapped to external module SEQ_IRQREQ interface.

 

 

TX1_ST <= Local_irq_req;   ....     JTAGEN <= Local_irq_req; --Local_SPI_Debug_Port(20); --SPI_MOSI1; -- LA 3 Local_Debug_PortW(3)  

 

RRomano001
New Contributor I
80 Views

changed pullup to pull down on microcontroller:

Confirm Pin is in default state 'Z'...

Pin state exported from module is in default state '0'.

 

Qsys or quartus or both?

changed order of code, cleaned project persist out.

Sorry don't ask inspect RTL, a bug on modelsim prevent from. I must hardwire some VHDL attribute 'high to do so. I cannot add subtle bug to my side.

RRomano001
New Contributor I
80 Views

Update:

Issue with interrupt gating never solved, I generated a workaround mapping unmasked interrupt signal to uController and managed it in software with some overhead till get solved.

Also reduced USART channel produce overhead to multiplexer, but this is the only solution I found about.

 

About pin found on HI Z, design stopped working on another core, so I realized the two USART interface where swapped by name on design.

After this both pin (LA and uController got driven low as expected.

Issue is still severe on internal at almost output pin driver still work same way on top level.

 

KennyT_Intel
Moderator
80 Views

Hi, I had email you another way so that you dont hardwire some VHDL attribute to high for your simulation. As the code itself got some pb where you cant compile it in modelsim.
KennyT_Intel
Moderator
80 Views

Not sure if you have update on this?
RRomano001
New Contributor I
80 Views

Hi Kenny, I stopped develop on this way for now.

I am preparing to test on Xilinx platform to get an Idea of where from are trouble.

Event passed with product not ready, I get time to decide what to do.

After Xilinx test two way open:

1 My design is faulty, so I have to say sorry. (work as is on Lattice platform)

2 Quartus and or MAX 10 is, this way a migration is required.

Regards

Roberto

KennyT_Intel
Moderator
80 Views

Got it, let us know how it goes.
Reply