MAX II and MAX V Metastability Analysis

[ZKami1]

My understanding is that the report_metastability feature of Quartus is not available for MAX II and MAX V devices. Does Altera provide a graph of MTBF vs. tMET or another way to manually perform metastability analysis for these devices?

[KhaiChein_Y_Intel]

Hi,

I am afraid that I have to inform you that the report_metastability is not supported in Max V and Max II devices and there is no document available for the metastability analysis.

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

[ZKami1]

Thanks for asking.

To give a little background on my project, I wanted to use only a single flip-flop synchronizer to synchronize an asynchronous input signal. Although a double-stage synchronizer would be preferable, power consumption as well as latency are both critical in my system. Double-synchronization of this signal would introduce an additional clock of latency, which would have to be compensated for by running at a faster clock speed, increasing power consumption.

My solution was to assume a tMET of 3 nanoseconds (very long for a 180nm device) and derate the timing of paths using the singly-synchronized signal by this amount. I was able to ensure that only a single LUT-4 preceded the D flip-flop for all registered signals which are a function of my singly-synchronized signal. In fact, Quartus says that my entire design can run at 125 MHz, with even more margin for the worrisome part fed from the single-stage synchronizer. We are only running at 60 or 66 MHz, so I think the likelihood that the output of the single-stage synchronizer staying metastable for the extra time it would take to cause a failure is extremely low.

I have run my system at 85 degC ambient or even higher for a while and have not observed any failures. In fact, even at 85 degC, the asynchronous propagation delay and setup times of the MAX II are quite good, as indicated by a substantial improvement in timing margin compared to our worst-case budget. We have also compared the timing of automotive-temperature-grade EPM240T100A5N to the commercial-temperature-grade EPM240T100C5N and we are not seeing much more than a nanosecond change in asynchronous propagation delay or clock-to-output time as temperature is increased from 25 degC to past 100 for either grade of chip. We have not tested faster speed grades. So we are fairly convinced that the MAX II is robust enough to support a single-stage synchronizer at 66 MHz. This is for a consumer electronic gizmo, so the MTBF is not too critical either. Nevertheless, it would be reassuring to have better MTBF data for the MAX II and MAX V.

[KhaiChein_Y_Intel]

Hi,

Thanks for the detailed update.

Thanks.

Best regards,

KhaiY