I purchased the Altera MAX10 FPGA Development Kit with the intent of experimenting with the DDR3 controller. After instantiating the IP and compiling the project I get the dreaded "Error (17044): Illegal connection on I/O input buffer primitive". This happens with Quartus 15.1 (recommended in the readme file for the kit), Quartus 16.1, whether I build the controller through the IP tool/catalog or through Qsys.There are a number of posts about this that date back to 2012, but nothing current, or relevant Presumably nobody is having problems with this lately. Any ideas?
After instantiating the DDR3 controller make sure you run the pin_assignment tcl script. Make sure it runs without errors. My problem arose because I was getting errors when I ran the tcl script. This was eventually traced to a mis-assignment of the ddr3_ck pins as outputs, rather than bidirectional (my error). BTW, after getting no response from this forum I filed a service request with Altera and got excellent, speedy support.