AN745 in "Table 1. I/O Standards for MIPI D-PHY Implementation" requires "Differential HSTL-1.8" for high speed pins. However Quartus compilation fails...
According to the MAX10 device handbook, the chip supports "Differential HSTL-1.8".
Is this feature available for all high speed pins?
thank you for your reply.
Indeed the document specify the VOL/VIH ranges, but it seems not referring to which set of IOs support Differential HSTL.
Is there any clarification on that?
Would all the pin marked as DIFFIO / DIFFIO_TX / DIFFIO_TX_RX support Differential HSTL?
thank you for the hint. For instance, that means pins marked
are not differential TX/RX but just differential RX capable pins, correct?
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