MAX10 Differential HSTL-1.8 for MIPI CSI2 TX

[luca5]

Hi,

AN745 in "Table 1. I/O Standards for MIPI D-PHY Implementation" requires "Differential HSTL-1.8" for high speed pins. However Quartus compilation fails...

https://www.intel.com/content/www/us/en/programmable/documentation/mcn1446711751001.html#mcn1448379540376

According to the MAX10 device handbook, the chip supports "Differential HSTL-1.8".

Is this feature available for all high speed pins?

Thank you

[AminT_Intel]

Hello,

Yes you can refer to page 22 from this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf

Thanks.

[luca5]

Hi AminT

thank you for your reply.

Indeed the document specify the VOL/VIH ranges, but it seems not referring to which set of IOs support Differential HSTL.

Is there any clarification on that?

Would  all the pin marked as DIFFIO / DIFFIO_TX / DIFFIO_TX_RX support Differential HSTL?

Thank you

[AminT_Intel]

Hello,

It depends. You may refer to pin-out files from this link of your device: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html

Thank you.

[luca5]

Hi Amin,

thank you for the hint. For instance, that means pins marked

DIFFIO_RX_L5n
DIFFIO_RX_L6n

are not differential TX/RX but just differential RX capable pins, correct?

Thank you

[AminT_Intel]

Hello,

Yes you are right!

Thanks

[AminT_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.