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This is what I find in the I/O Assignment Warnings:
This is the list in pin planner:
The assignment editor:
And the top vhdl:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Counter_pack.all;
entity counter is
port (
ResetxSBI : in std_logic;
ClkxCI : in std_logic;
LedxDO : out std_logic_vector(7 downto 0)
);
end counter;
architecture behavioral of counter is
signal CountValuexD : unsigned(COUNTER_WIDTH-1 downto 0); -- count value
begin
CntStateMachine: process (ClkxCI,ResetxSBI)
begin
if ResetxSBI = '0' then
CountValuexD <= to_unsigned(0,COUNTER_WIDTH);
elsif ClkxCI'event and ClkxCI = '1' then
-- determine next counter value
CountValuexD <= CountValuexD + to_unsigned(1,COUNTER_WIDTH);
end if;
end process CntStateMachine;
-- assign outputs
LedxDO <= std_logic_vector(CountValuexD(COUNTER_WIDTH-1 downto COUNTER_WIDTH-8));
end behavioral;The mesage incomplete set of assignments seems to refer to the only two inputs of the design. The outputs seem to be OK. But I don't understand what's missing.
