MAX10 FPGA Pin Assignments for LVDS signals input and outputs

[NM8]

Hi,

We are using MAX10 FPGA(10M40SCE144C8G) with our board. We want to connect multiple input and output LVDS signals to one of the banks of this FPGA.

To use the true LVDS (TX or RX) should we use 2.5V as VCCIO or we can use 3.3V? Note that, we have both single ended (3.3V LVCMOS) and differential IO signals in the same bank.

When we compile with the same design with Quartus prime, its failing.

But when we remove the single ended signals from Quartus project.

Can anyone please help me with this issue.

Thanks & Regards,

Nanjunda M

[Abe]

You cannot assign a single IO bank with both 3.3V and 2.5V IO standards. If you assign Bank1 for 2.5V IO then all the IO in this bank will share the same IO standard. This is coz the VccIO for that particular Bank will have to be set to 2.5V.

You will have to assign the 2.5V and 3.3V signals to different IO banks and then compile. Plus also make sure that the IO bank you are planning to use for LVDS does support the LVDS standard (True-LVDS/BLVDS/Emulated LVDS/mini-LVDS/etc). As far as I know, true LVDS is supported only in Bank3 for Max10 devices. Check the data sheets for LVDS support and IO Bank support.

[NM8]

Hi Abe,

My Question is whether I can use a True LVDS in bank with VCCIO = 3.3V?

"Plus also make sure that the IO bank you are planning to use for LVDS does support the LVDS standard (True-LVDS/BLVDS/Emulated LVDS/mini-LVDS/etc"

Yes Its only for the TX and not for the RX. True RX is supported in all the Banks & TX count varies based on the device size.

Kindly can anyone let me know have used a True-LVDS TX & RX (Any bank in MAX10FPGA) with VCCIO supply 3.3V?

Thanks & Regards,

Nanjunda M

[Abe]

Yes, you can. I have compiled an LVDS design using both LVDS Tx & Rx @ Bank3 and IO Standard set to 3.3 V LVCMOS. But make sure to set all other pins in the same Bank to the same voltage standard.

The design I used has single-ended signals also at the same bank set to 3.3V LVCMOS.

Can you post the compilation report file here.. so we can take a look and see whats wrong. As well as the pin assignments file QSF.

[NM8]

Hi Abe,

Thanks a lot for your inputs.

"I have compiled an LVDS design using both LVDS Tx & Rx @ Bank3 and IO Standard set to 3.3 V. But make sure to set all other pins in the same Bank to the same voltage standard."

I tried the same thing. My experiment results are as below:

1. With just LVDS TX & RX with VCCIO=3.3V - Compilation passed
2. Along with '1' I added 1 input single ended (defined as 3.3V LVCMOS in Assignment editor) signal to the same bank - Compilation passed
3. Along with '2' I added 1 output single ended (defined as 3.3V LVCMOS in Assignment editor) signal to the same bank - Compilation failed.

Got an error saying there is no IO voltage compatibility between the IO pins.

According to your statement above, we are still working all at 3.3V level, yet we get a error which says we are not right.

Could you give me some confirmation on this please?

Thanks & Regards,

Nanjunda M

[Abe]

Can you post the compile log , the actual error message as well as the Pin assignments you've used. It's not easy debugging without this information.

[NM8]

Hi Abe,

FYI the project is attached. You can compile it and check.

The errors are as below:

""Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

Warning (176674): Following 2 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.

 Warning (176118): Pin "MX_REFCLK_100MP" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "MX_REFCLK_100MP(n)"

 Warning (176118): Pin "CE2_MX_CLKP" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "CE2_MX_CLKP(n)"

Error (169236): Can't place I/O pin Extr1 in assigned location IOBANK_2 made by User Location Constraints source

 Error (169027): Pin Extr1 is incompatible with I/O bank 2. Pin uses I/O standard 3.0-V LVCMOS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or other pins that use I/O standard LVDS.

Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00

Error (171000): Can't fit design in device

Warning (169177): 1 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.

 Info (169178): Pin MXFPGA_RESETIN uses I/O standard 3.3-V LVCMOS at 27

Warning (169069): Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results

 Info (169070): Pin Extr1 has GND driving its datain port

Error: Quartus Prime I/O Assignment Analysis was unsuccessful. 3 errors, 9 warnings

 Error: Peak virtual memory: 5003 megabytes

 Error: Processing ended: Tue Mar 05 13:36:59 2019

 Error: Elapsed time: 00:00:02

 Error: Total CPU time (on all processors): 00:00:02"

Thanks & Regards,

Nanjunda M

[Abe]

Well, I just took a look at your pin assignments and see that you have assigned a single IO Bank (Bank 2) with both 3.3V LVCMOS as well as 3.0V LVCMOS. This is a violation of the Bank IO standard rule I mentioned earlier.

You can only assign one IO standard/voltage to a Bank. Assign the single-ended pins that need a different voltage standard , for eg, 3.0V or 2.5V to another bank and assign the pins accordingly.

 

Either Change the voltage standard for the EXTR1 pin to 3.3V LVCMOS or move to another Bank and Pin location.

[NM8]

Hi Abe,

Sorry for that. Can you please change the standard to 3.3V LVCMOS and assign any pin in same bank(bank2) and compile.

You will see the error I have stated in previous email. I have tried, (Do not forget to check the pin assignment if the compilation passes)

Kindly try once and let me know the results of compilation.

Thanks & Regards

Nanjunda M

[Abe]

Hi,

The issue is due to the limited number of pins for each bank in the E144 package of Max10 device you're using, each bank can be assigned only a single IO Voltage standard as well as IO Standard.

Since you've assigned Bank2 as 3.3V LVCMOS and LVDS IO Standard, the IO Buffers in the device for Bank2 are configured as LVDS IO buffers. These can accept single-ended signals as inputs but cannot output single-ended signals.

The error message says whats wrong:

Error (169027): Pin Extr1 is incompatible with I/O bank 2. Pin uses I/O standard 3.3-V LVCMOS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or other pins that use I/O standard LVDS.

If you look at your pin-outs, the other single-ended signal in the same bank (Bank2) is an input, along with two LVDS input clocks. So this is okay. But when you assign output signal which is single-ended to the same LVDS bank, the IO buffer cannot drive the same as single-ended.

What you need to do is to assign any single-ended output signals in your design to other banks that are configured as 3.3V LVCMOS and non-differential. Assigning the same EXTR1 output to IO Bank 1B just above Bank2 solves the issue and the compile goes through.

These are the limitations when working with different IO voltages and standards on FPGA devices that you have to keep in mind when assigning pins. Please read the IO documentation before making any pin assignments.

[NM8]

Hi Abe,

"Since you've assigned Bank2 as 3.3V LVCMOS and LVDS IO Standard, the IO Buffers in the device for Bank2 are configured as LVDS IO buffers. These can accept single-ended signals as inputs but cannot output single-ended signals."

• Does it mean that I do not have to give a 2.5V supply for the LVDS signals (i.e. to VCCIO).

Am I correct to understand that I can implement any LVDS signals in 3.3V bank but with limitation as no 3.3V single ended output signals are allowed in that bank.

If above statement is right, what would be the common mode voltage of the LVDS signals(from 3.3V bank voltage)?

As per the datasheet, the LVDS signals are defined only with VCCIO=2.5V in the table.

Thanks & Regards,

Nanjunda M

[NM8]

Hi

Does anyone tell me whether my above statement is correct or wrong?

Thanks & Regards,

Nanjunda M

[Abe]

Well, I wouldn't suggest you use 3.3V for LVDS . When using LVDS you will have to check the operating voltage / current of the device on the other side (Tx/ Rx) and match the IO standard to that on the FPGA. Ideally, LVDS would be 2.5V and lower as its a Low-Voltage Signalling standard and 3.3V is not considered low-voltage.

My suggestion is to go with 2.5V for LVDS as most LVDS based devices would be operating at this voltage level. But as mentioned above, always check the data sheet of the other LVDS components and then set your IO standard, Slew Rate, etc.

[NM8]

Well, I understand your point.

But If I use the VCCO as 3.3V and connect the LVDS signals and assign them as LVDS 2.5V in Quartus, what exactly the output voltage would be (on LVDS signal) ?

Has anyone tried this ? How exactly the FPGA is going to behave with this?

Thanks & Regards,

Nanjunda M

[Vicky1]

Hi Nanjunda, I tried to replicate scenario & I observed the below results,please try to implement same at your end & if you have any different issue let me know, please find the below link & attachments, https://www.intel.com/content/www/us/en/programmable/documentation/sam1394433606063.html#sam1394435423058 Regards, Vikas

[NM8]

Hi Vikas,

Not sure what you are referring to in the link above.

Are you referring to "Intel MAX 10 LVDS SERDES I/O Standards Support " heading?

I do want to use the True LVDS & I'm clear with the pins to be used for it.

Just that confusion whether to give VCCO=2.5V or 3.3V.

I hope you can clear it. If you recommend to use 2.5V, why not 3.3V and what would be the signal characteristics with 3.3V VCCO.

Thanks & Regards,

Nanjunda M

[Vicky1 · Accepted solution]

Hi Nanjunda,

I tried to replicate scenario & I observed the below results,please try to implement same at your end & if you have any different issue,let me know,

please find the below link & attachments,

https://www.intel.com/content/www/us/en/programmable/documentation/sam1394433606063.html#sam1394435423058

Regards,

Vikas