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Beginner
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MAX10 GPIO Lite DDR Output Sim

I've run into the follow error while initializing an Aldec simulation:

 

ELBREAD: Error: ELBREAD_0081 fiftyfivenm_atoms_ncrypt.v (732): Design unit protected_97b98e91bb4cae2ac97c0cd96c2469e5 instantiated in fiftyfivenm_ver.protected_c1a23861916f90f6e0d08a9e524674ac1a53e8ab8a67ecf4fe70c175c8a05438 not found in searched libraries: fiftyfivenm_ver, MaxGpioSim.

 

I have been successful simulating a gpio lite input (single FF).

 

Any help would be greatly appreciated.

Thanks

-Brian

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Valued Contributor II
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Have you compiled the device libraries for Aldec simulator using Quartus Library compiler prior to performing the RTL simulation ? Try re-compiling the FPGA libraries and then simulating.

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Hi Brian,

 

Please note the version of ALDEC simulator tested with Quartus.

https://www.intel.com/content/www/us/en/programmable/documentation/gtt1529956823942.html

Table 1. Supported Simulators

 

Since you mentioned you are able to simulate GPIO Lite Single input FF, I am suspecting above Error message is due to missing Libraries

Can you try following.

  • Use the auto-generated simulation script to bring up IP simulation.

If the issue still persists you can share further details with me to take a look.

  • Quartus Version used to Generate IP and simulation libraries.
  • What version of ALDEC simulator are you using ?
  • GPIO settings (If possible share the project archive)
  • What steps did you followed to replicate Error ?

 

Thanks,

Arslan

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Beginner
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I have already tried to use the auto-generate simulation script which creates and compiles all of the required libraries.

I've also tried the pre-compiled Aldec libraries. Same results in both cases.

When the issue first started I was using Active-HDL 10.3 and Quartus 17.0.

Then I updated to the latest of both tools: Active-HDL 10.5a.12.6914 and Quartus 18.1.0

 

gpoutputddr_inst : component altera_gpio_lite

generic map (

PIN_TYPE                 => "output",

SIZE                   => 1,

REGISTER_MODE              => "ddr",

BUFFER_TYPE               => "single-ended",

ASYNC_MODE                => "clear",

SYNC_MODE                => "none",

BUS_HOLD                 => "false",

OPEN_DRAIN_OUTPUT            => "false",

ENABLE_OE_PORT              => "false",

ENABLE_NSLEEP_PORT            => "false",

ENABLE_CLOCK_ENA_PORT          => "false",

SET_REGISTER_OUTPUTS_HIGH        => "false",

INVERT_OUTPUT              => "false",

INVERT_INPUT_CLOCK            => "false",

USE_ONE_REG_TO_DRIVE_OE         => "false",

USE_DDIO_REG_TO_DRIVE_OE         => "false",

USE_ADVANCED_DDR_FEATURES        => "false",

USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY => "false",

ENABLE_OE_HALF_CYCLE_DELAY        => "true",

INVERT_CLKDIV_INPUT_CLOCK        => "false",

ENABLE_PHASE_INVERT_CTRL_PORT      => "false",

ENABLE_HR_CLOCK             => "false",

INVERT_OUTPUT_CLOCK           => "false",

INVERT_OE_INCLOCK            => "false",

ENABLE_PHASE_DETECTOR_FOR_CK       => "false"

)

port map (

outclock    => outclock, -- outclock.export

din       => din,   --   din.export

pad_out     => pad_out, -- pad_out.export

aclr      => aclr,   --   aclr.export

outclocken   => '1',   -- (terminated)

inclock     => '0',   -- (terminated)

inclocken    => '0',   -- (terminated)

fr_clock    => open,   -- (terminated)

hr_clock    => open,   -- (terminated)

invert_hr_clock => '0',   -- (terminated)

phy_mem_clock  => '0',   -- (terminated)

mimic_clock   => open,   -- (terminated)

dout      => open,   -- (terminated)

pad_io     => open,   -- (terminated)

pad_io_b    => open,   -- (terminated)

pad_in     => "0",   -- (terminated)

pad_in_b    => "0",   -- (terminated)

pad_out_b    => open,   -- (terminated)

aset      => '0',   -- (terminated)

sclr      => '0',   -- (terminated)

nsleep     => "0",   -- (terminated)

oe       => "0"    -- (terminated)

);

 

Thanks for the support!

-Brian

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Beginner
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Hi All,

 

I just solved this issue by adding altera_ver to the Verilog Libraries (-L) which is used by asim.

Not sure why this is was needed but a least now I can make progress.

 

Thanks

-Brian

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Hi Brian,

 

"altera_ver" is a Altera simulation library for Verilog similarly there is one for VHDL "altera" and is needed to simulate the IP. I am wondering if this is not part of auto-generated script.

 

I am glad you are able to proceed.

 

Thanks,

Arslan

 

 

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