MAX10 Same Code Fitting Differently Each Time

[ashbinbabu]

Hi,

We are using MAX10 in our server motherboard. Let's say our code has 3 main sections - A, B and C. Whenever I am making a small change in Section C, the working of Code in Section A and B are changing on compilation. There are no common signals at all b/w the 2. Sometimes, simply compiling the same code multiple times result in different behavior in the hardware on programming. We are completely unaware on how to correct this issue of same code behaving differently on compiling again and again. We suspect this had got to do something with how the code is fitted into the silicon. MAX10 doesn't support Rapid Compilation also.

Awaiting response from anyone who could help us in this regard.

Regards,

Ashbin

[sstrell]

Any time code is changed, a new "seed" is used for the compilation which can produce different results.  Is something changing that is causing your design to not work when you recompile (timing failure, inappropriate resource usage, etc.)?  If so, it may be better to look and try to debug the issue instead of relying on compiling with a seed that meets your requirements.

[ashbinbabu]

Like I said, sometimes simply recompiling without touching the code is also producing different results on fusing to the FPGA. This is what troubles us the most. How can this be avoided? Let us know what settings to use to prevent this.

[RichardTanSY_Intel]

Which Quartus version are you using? Could you try using the latest Quartus version to check if the issue persists?

For reference, the KDB article below outlines the factors required to achieve identical results across compilations:

https://www.intel.com/content/www/us/en/support/programmable/articles/000084189.html

Additionally, I recommend using incremental compilation to preserve placement and routing results for specific portions of your design:

https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/best-practices-for-incremental-compilation.html

Regards,

Richard Tan

[ashbinbabu]

We are using Quartus Prime Lite edition 18.1.1 Build 646 with patch 1.01. This version is required for implementing Intel PFR. We can try with pro version -  that's the only option left. Since our code is almost finalized, implementing incremental compilation will be quite difficult at this stage as it calls for changes in code structure itself I believe. In the first link shared, it is mentioned "Even changes in comments" can result in different results.

Let us know if there is any other workaround. 

[RichardTanSY_Intel]

Yes, even adding a comment might change the tool's fitter seed/variation.

If you're interested, you can check out this white paper on the fitter algorithm:

https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset01/fittingalgorithms-and-seedsweeps.pdf

Other than using incremental compilation and logic lock, I don't think there's another way to keep other modules unchanged without using design partitioning.

If you don't plan to make further changes to the module, exporting the database could be a way to preserve the compilation results.

Regards,

Richard Tan

[ashbinbabu]

Can you let us know what you meant by logic lock? MAX 10 doesn't support exporting database. 

Regarding Seeds - We tried running design space explorer with different seed sweep and found that seed=6 has a better quality of fit. We want to try with 6 as the initial seed in our fitter settings. Let us know if this approach is correct or not.

[RichardTanSY_Intel]

You may checkout this user guide for further details on logic lock.

https://www.intel.com/content/www/us/en/docs/programmable/683230/18-1/regions.html

If seed = 6 yielded the best results, you can use it as the initial fitter placement. However, keep in mind that modifying the design or Quartus settings even slightly will usually change which seed is best for the design.

Regards,

Richard Tan

[RichardTanSY_Intel]

Hi

Do you need any further assistance from my side?

Regards,

Richard Tan

[RichardTanSY_Intel]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

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Best Regards,

Richard Tan