MAX10 fiftyfivenm Gate level Simulation ** Error: (vsim-3033) and no timing simulation.

[BrianHG]

Hello,

I'm using Quartus 20.1.  I have a design which I wish to inspect and verify the gate level simulation.  I have no trouble with a CycloneIV FPGA, but with Max10, once modelsim starts up, it gives me this error:

# Loading fiftyfivenm_ver.fiftyfivenm_pll
# Loading fiftyfivenm_ver.fiftyfivenm_m_cntr
# Loading fiftyfivenm_ver.fiftyfivenm_n_cntr
# Loading fiftyfivenm_ver.fiftyfivenm_scale_cntr
# Loading fiftyfivenm_ver.fiftyfivenm_ddio_in
# Loading fiftyfivenm_ver.fiftyfivenm_ddio_out
# Loading fiftyfivenm_ver.fiftyfivenm_routing_wire
# Loading fiftyfivenm_ver.fiftyfivenm_mux21
# Loading fiftyfivenm_ver.fiftyfivenm_ddio_oe
# ** Error: (vsim-3033) Instantiation of 'fiftyfivenm_termination' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /BrianHG_DDR3_DECA_test1_top_tb/BHG_DDR3_DECA_test1_top File: BrianHG_DDR3_DECA_test1_top.svo Line: 56658
# Searched libraries:
# C:/intelFPGA_lite/20.1/modelsim_ase/altera/verilog/altera
# C:/intelFPGA_lite/20.1/modelsim_ase/altera/verilog/altera_lnsim
# C:/intelFPGA_lite/20.1/modelsim_ase/altera/verilog/fiftyfivenm
# C:/altera/Qdesigns/BrianHG_DDR3_DECA_test1/simulation/modelsim/gate_work
# C:/altera/Qdesigns/BrianHG_DDR3_DECA_test1/simulation/modelsim/gate_work
# Loading fiftyfivenm_ver.fiftyfivenm_pseudo_diff_out
# Loading fiftyfivenm_ver.fiftyfivenm_unvm
# Loading fiftyfivenm_ver.fiftyfivenm_adcblock
# Error loading design
# Error: Error loading design

Is there something I am missing?  The FPGA does compile and it does RTL simulate.

[SyafieqS]

Hi Brian,

You may need to look at the following KDB

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06282010_469.html