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MAX10 fiftyfivenm Gate level Simulation ** Error: (vsim-3033) and no timing simulation.

BrianHG
New Contributor I
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Hello,

I'm using Quartus 20.1.  I have a design which I wish to inspect and verify the gate level simulation.  I have no trouble with a CycloneIV FPGA, but with Max10, once modelsim starts up, it gives me this error:

# Loading fiftyfivenm_ver.fiftyfivenm_pll
# Loading fiftyfivenm_ver.fiftyfivenm_m_cntr
# Loading fiftyfivenm_ver.fiftyfivenm_n_cntr
# Loading fiftyfivenm_ver.fiftyfivenm_scale_cntr
# Loading fiftyfivenm_ver.fiftyfivenm_ddio_in
# Loading fiftyfivenm_ver.fiftyfivenm_ddio_out
# Loading fiftyfivenm_ver.fiftyfivenm_routing_wire
# Loading fiftyfivenm_ver.fiftyfivenm_mux21
# Loading fiftyfivenm_ver.fiftyfivenm_ddio_oe
# ** Error: (vsim-3033) Instantiation of 'fiftyfivenm_termination' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /BrianHG_DDR3_DECA_test1_top_tb/BHG_DDR3_DECA_test1_top File: BrianHG_DDR3_DECA_test1_top.svo Line: 56658
# Searched libraries:
# C:/intelFPGA_lite/20.1/modelsim_ase/altera/verilog/altera
# C:/intelFPGA_lite/20.1/modelsim_ase/altera/verilog/altera_lnsim
# C:/intelFPGA_lite/20.1/modelsim_ase/altera/verilog/fiftyfivenm
# C:/altera/Qdesigns/BrianHG_DDR3_DECA_test1/simulation/modelsim/gate_work
# C:/altera/Qdesigns/BrianHG_DDR3_DECA_test1/simulation/modelsim/gate_work
# Loading fiftyfivenm_ver.fiftyfivenm_pseudo_diff_out
# Loading fiftyfivenm_ver.fiftyfivenm_unvm
# Loading fiftyfivenm_ver.fiftyfivenm_adcblock
# Error loading design
# Error: Error loading design

 

Is there something I am missing?  The FPGA does compile and it does RTL simulate.

 

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SyafieqS
Employee
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roboknave
Novice
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I noted that the reply to this question points to something quite old as it refers to Quartus 10.  I'm have a very similar problem, but it appears it might be related to verilog files that are protected IP.  It appears that the tools can't tell this and it always shows up as "Macro `<protected> is undefined".  I was trying to use the library compiler to compile a trivial design for the MAX10 under Quartus 21.1.  It is unclear what the last version of Quartus to officially support the MAX10 is, but it might be 18.  I know I downloaded the MAX10 files into Quartus 21.1, and while it does build designs for the MAX 10, simulation does not seem to be possible here as no matter which way I turn, I get some kind of horrendous error.  At any rate, if this *ISN'T* a similar problem, I just need to be pointed to where someone who might actually know how to fix them problem would be able to help me.

 

Regards.

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