Hello all,I am trying to simulate the Avalon ST Demultiplexer (and corresponding multiplexer) in ModelSim but only get zeros as output signals. My problem is that signals go in, but I have figured they seem to stop at some internal submodule called an "inpipe." This "inpipe" is instantiated by "nios_system_demultiplexer_0_1stage_pipeline" and always outputs zero on it's signals. I tried looking for the Verilog for this module but cannot find it on my disk. Perhaps Quartus includes "nios_system_demultiplexer_0_1stage_pipeline"on the compile? I don't see it on disk. Am I missing something? Is there a better way to simulate the Avalon ST Demultiplexer or Avalon ST Multiplexer. I've attached a screenshot of the signals as well as a copy of the DEMUX verilog code. The DEMUX module I instantiated has 1x Avalon-ST-Sink interface, and 5x Avalon-ST-Source outputs. Output ready signals tied to 1 to simulate a receiving sink being always ready.
I believe I have found an answer for all those who might search for it: It is simply not provided for by Altera.Chapter 18 of the UG-01085 Embedded Peripherals IP User Guide (2016) says the following: --- Quote Start --- Hardware Simulation Considerations The multiplexer and demultiplexer components do not provide a simulation testbench for simulating a stand-alone instance of the component. However, you can use the standard SOPC Builder simulation flow to simulate the component design files inside an SOPC Builder system. --- Quote End --- It is thus not possible to simulate an isolated extraction of either the multiplexer or demultiplexer components.