MODELSIM: Error: (vsim-13) Recompile work

[BDarji]

I am having certain System Verilog files. Some of them contain packages. Those are included in other files. I was trying to simulate them using Modelsim - INTEL FPGA Started Edition. Although compilation was successful, while trying to start simulation, I was getting following error messages:

# vsim work.tb_tx_phy

# Start time: 12:29:30 on Apr 09,2020

# ** Error: (vsim-13) Recompile work.tb_tx_phy_sv_unit because work.u11h_reg_pkg, work.u11h_usb_pkg have changed.

# ** Error (suppressible): (vsim-12) Recompile work.tb_tx_phy after work.tb_tx_phy_sv_unit is recompiled.

# ** Error: (vsim-13) Recompile work.tb_tx_phy because work.u11h_reg_pkg, work.u11h_usb_pkg have changed.

# Error loading design

# End time: 12:29:31 on Apr 09,2020, Elapsed time: 0:00:01

# Errors: 3, Warnings: 0

[BDarji]

With the help of my colleague, I was able to solve this problem in following way:

1. First compile all files.
2. From Library tab, right click on 'work' and select refresh. (See the attached image.)
3. Now, start simulation.

While searching for this, I spent couple of hours. But didn't get succeed until got work-around or solution from my colleague.

Anyway, I hope this would be useful to someone in future.

Cheers,

Bhaumik

[Sergeybond]

Thank you! Thing with Refresh button actually worked

[Kenny_Tan]

Thanks, this will be very useful especially using the refresh button.