Sometimes we have observed that our custom component (having _hw.tcl file) does not appear in Platform Designer (Qsys) IP library even after providing IP core search path via Qsys>Tools>Options>IP Search path option.
There could be other alternative for this. But based on our experience, we have prepared one document which could help you in such a case. We have attached it herewith. We hope this would be useful to someone in future.
One shall also refer Dave's answer provided here regarding IPX file : QSYS Custom component not found - Intel Community
Our approach is similar to that.
Thank you and Have a Great Day!
Thank you for your response.
I am facing issue with Quartus 18.1 Standard edition. But, in past, we faced similar type of issue with older Quartus version as well. And, that's what led us to find out some work-around for this!
Basically we are designing IP cores, mainly USB IP cores. Although other IP cores are in encrypted form, we have I2C master IP core which we are providing free of charge. If you can give me your email ID, I can request our sales team to share that component to you. It will contain RTL files as well as hw.tcl file. I am facing same issue with that as well. Hence, you can check at your end whether same issue is happening with you or not.
You don't mention any error messages or any other info about why your components aren't showing up in the IP Catalog, but my guess is that the connection between the _hw.tcl file and your custom component HDL code is getting lost. This can happen if you use the Platform Designer Component Editor and then move the _hw.tcl file from the project directory and/or the HDL code.
In recent versions of Platform Designer (probably within the last 3-4 years), the _hw.tcl file from the Component Editor always gets created at the location of the .qsys file, not at the location of the HDL code you point to in the Component Editor, which is what it used to do. As such, if you move either the _hw.tcl or the HDL code, even if you point PD to the location of the _hw.tcl, it won't work.
What you have to do is edit the _hw.tcl file, wherever you've moved it to and edit the following:
add_fileset_file <file>.[v|vhd] [VERILOG|VHDL] PATH <file_path> [TOP_LEVEL_FILE]
If you set the path correctly and then refresh PD (F5 key or menu command), it should work.
Hello @sstrell ,
Thank you very much for your response and sorry for delay.
You are right that initially we use Platform Designer Component Editor to create _hw.tcl file and then are moving it to other location. But we are moving RTL files along with _hw.tcl file. And hence, RELATIVE path remains same.
In our case, we are used to place RTL files in hdl folder and _hw.tcl file remains in same folder in which hdl folder resides. Then, we are using following commands to add files.
add_fileset_file ./sls_i2c_mstr/i2cc_wrapper.sv SYSTEM_VERILOG PATH ./hdl/i2cc_wrapper.sv TOP_LEVEL_FILE add_fileset_file ./sls_i2c_mstr/i2cc_user_define.pkg.sv SYSTEM_VERILOG PATH ./hdl/i2cc_user_define.pkg.sv add_fileset_file ./sls_i2c_mstr/i2cc_dp_ram_mf.v VERILOG PATH ./hdl/i2cc_dp_ram_mf.v
Do you see any issue in this?
Thank you and Have a Nice Day!
Hello @sstrell ,
Thank you for your response and continuous support.
I do not think that relative path is an issue here because of following reasons:
(1) Please refer following image. It states we can either use absolute or relative path.
(2) Note that if we use 'user_component.ipx' file method I described in initial post, there is no issue. RTL files are generated properly when Qsys system is generated. Hence, I think file path is fine.
What do you think?
Have a Nice Day!
Hello @sstrell ,
Sorry for delayed response. And thank you for your response.
I have tried absolute path. Please have a look at following:
add_fileset_file ./sls_i2c_mstr/i2cc_wrapper.sv SYSTEM_VERILOG PATH "E:/designs/sls/i_i2cc/trunk/master/software/setup/resources/i2c_mstr/hardware/component/hdl/i2cc_wrapper.sv" TOP_LEVEL_FILE add_fileset_file ./sls_i2c_mstr/i2cc_user_define.pkg.sv SYSTEM_VERILOG PATH "E:/designs/sls/i_i2cc/trunk/master/software/setup/resources/i2c_mstr/hardware/component/hdl/i2cc_user_define.pkg.sv" add_fileset_file ./sls_i2c_mstr/i2cc_dp_ram_mf.v VERILOG PATH "E:/designs/sls/i_i2cc/trunk/master/software/setup/resources/i2c_mstr/hardware/component/hdl/i2cc_dp_ram_mf.v"
But unfortunately it didn't help.
I have attached herewith one text file which shows messages which are generated by Qsys when we refresh system. See whether this gives any clue or not.