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Map multipliers to DSP blocks using Quartus 18.0



I want to map multipliers to the Arria 10 DSP blocks using Quartus 18.0 Pro.

I'm using the following code from the template:


module teste

#(parameter WIDTH=18)


   input clk,

   input signed [WIDTH-1:0] dataa,

   input signed [WIDTH-1:0] datab,

   //input rst_n,

   //input enb,

   output reg signed [2*WIDTH:0] dataout


   // Declare input and output registers

   reg signed [WIDTH-1:0] dataa_reg;

   reg signed [WIDTH-1:0] datab_reg;

   wire signed [2*WIDTH:0] mult_out;

   // Store the result of the multiply

   assign mult_out = dataa*datab;

   // Update data

   always @ (posedge clk)


    dataout <= mult_out;



The problem is: Quartus 18.0 doesn't map the multiplier to dsp block and give the following message: Warning(16229): One or more output registers failed to be packed into a DSP bank due to multiple fan-outs from the DSP block. Because that doesn't register the output.

When I use the same code or others code in Quartus 17.1.0, it maps the multiplier to a DSP block with a registered output.

Why Quartus 17.1 maps the multiplier to a DSP block and Quartus 18 don't?

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4 Replies



As I checked with the Q18.0Pro Help, it seems to say the following:



CAUSE: A DSP block output port with multiple fan-outs prevented some registers from being packed inside the DSP block.

ACTION: Please refer to "Fixed Point DSP Register Packing Details" table in the Fitter Report to determine which DSP blocks were affected. Ensure DSP block outputs that require register packing have only one fan-out.



Can you help to check if the fan-out restriction apply to your design? Here, it seems to say the output can only have one fan-out. If after modifying your design to have one fan-out and it can pass the compilation, this might be relate to new restriction in Q18.0Pro on register packing.


Thank you.



Hi cpchan,


Thank you for your help. I solved the fan-out problem but Quartus still doesn't map the multiplier to DSP block. The warning now is: Warning(16226): One or more registers failed to be packed into a DSP bank due to a Quartus or user restriction

Warning(16067): 1 out of 1 DSP blocks in the design are not fully utilizing recommended internal DSP register banks. Design performance may be limited. To take full advantage of device resources, you should either enable the register banks directly (if using WYSIWYG entry) or provide additional registers in your design that the Quartus register packing optimization algorithm can convert to internal DSP register banks. See "Fixed Point DSP Register Packing Details" fitter report . Remember that in Quartus 17 with the same code maps the multiplier to DSP block with the output registered.

Hi, Sorry for the delay. Just would like to check with you if you have had a chance to try using the DSP Native IPs to implement your design to see if similar observation occurs? To avoid gating your progress, it is recommended for you to continue using the Q17.1 which is working while debugging on this. Sorry for the inconvenience. Best regards, Chee Pin
New Contributor I

The inference engines can be finicky and change from rev to rev. Why not just use:

always @ (posedge clk) begin dataout <= dataa*datab; end

I use the VHDL version and it infers signed * signed and unsigned * unsigned just fine. For signed*unsigned it fails.