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Beginner
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Master data width is more than slave data width in Qsys AXI bridge

Hi all!

Currently I am working in Quartus 17. I have created AXI bridge-based system in the Qsys, where data bus for both master and slave sizes is 32-bit. Now I need to increase AXI bridge data width to 128 bit (master side), but some of my slave devices have 32-bit data bus. I have found in "Qsys Interconnect" pdf (chapter 7, pp.61) that this situation (master data width > slave data width in AXI Bridge) is not supported by Qsys (is it right?). So, the question is how to handle this situation?

Thank you in advance!

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Hi,

 

You can refer here on AXI Bridges sections on page 9.

 

Regards.

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Moderator
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I don't think the HPS bridges are the question here.

 

Can you specify which document you are referring to here? Different data widths between master and slave should be handled automatically when the interconnect is generated. I don't recall that this is an issue for Avalon or AXI. I don't know if you are using the Standard or Pro edition of the software, but here is the latest Platform Designer user guide for the Standard edition:

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-platform-designer...

 

#iwork4intel

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To create a custom component (or Intellectual Property (IP)) that functions using AXI bridge in Qsys, click the title below for the training video:

 

Custom Component Development Using Avalon® and Arm* AMBA* AXI Interfaces

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Beginner
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Hi, thank you for your answer!

I have found this document - https://www.coursehero.com/file/31922700/qsys-interconnectpdf/ (see pp.61).

Yes, data width will be adjusted automatically when master data width < slave data width.  I have found in this document that opposite situation (master data width > slave data width in AXI Bridge) is not supported by Qsys (is it right or I am mistaken?)

Actually, I tried to generate Qsys with master data width > slave data width, and it doesn't work right.

 

 

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