Meeting timing closure for externally clocked synchronous interface (FT2232)

Altera_Forum · ‎12-10-2010

Hi!

I'm trying to meet timing closure on a Cyclone-3 EP3C55F484C8 talking to a FTDI USB chip, FT2232H, using their "Synchronous FT245" mode. This simply means that they send a 60 mhz clock to me, and I have to synchronize for example the WR and DATA signals to the chip to this.

60 mhz is 16.666 ns period and the FT2232H specifies a massive *11 ns* of setup time for WR and DATA to the posedge clk.

Doing this trivial test does not pass TimeQuest:

   always_ff @ (posedge usb_clk) begin
      usb_wr <= ~usb_wr;
   end

with these constraints:

create_clock -period "16.666 ns" -name {usb_clk} {usb_clk}
#  USB Synchronous-245-mode FTDI2232H
set ftdi_rdwr_setup 11.0
set ftdi_rdwr_hold 0.0
set ftdi_pcb 0.5
set ftdi_clkskew 0.3
set_output_delay -clock { usb_clk } -max  
		 
set_output_delay -clock { usb_clk } -min

PCB and clkskew values are just made up.

The clock delay + data delay is too long for the usb_wr register compared to the latch edge of usb_clk by at least 2 ns creating a setup violation.

Apart from the fact that this seems a bit slow to me, any suggestions on how to normally handle this? I tried attaching a PLL and tried 0, 90 and 270 degree phases but for the 270 degree, which theoretically would give me 4.15 more ns of setup slack, I think I need to add a cycle of delay otherwise the margin shrinks even more (since it creates a launch->latch edge of 4.15 ns only). I'm a noob at that type of constraint modification so I thought I'd ask what the "right" way is to solve this before fixing that but I guess I'll go try it in the meantime :)

Best regards

/Bjorn

Altera_Forum · ‎12-10-2010

Ok, I realized that shifting the clock too much obviously violated the hold-relationship so I had to relax it a bit from the 90 degree shift.

I got it to work by shifting for example -25 degrees and adding a multicycle of 2 between the PLL input clk and output pin clk so TQ does not consider the first edge after the shift to be the latch edge. I guess this is the Right Way to do this after all?

/Bjorn

Altera_Forum · ‎12-10-2010

Use dual edge design. Feed 60 MHz into PLL, multiply by 2 to 3. That gives 120 MHz to 180 MHz resolution.