Megafunction wizard VHDL error?

Altera_Forum · ‎04-02-2012

Hello, I am currently working on a processor project for school, and have run into an issue where one of the megafunction-generated VHDL files seems to have an error in it, and I was wondering if anyone on here could help figure out what is causing it. I dont really know much VHDL, so I was wondering if someone could explain to me why this isnt working. Also, I have not edited the VHDL file at all. Any help would be great!

Error: Text Design File syntax error: Text Design File contains MEMORY where a symbolic name or a number was expected

VHDL File:

-- megafunction wizard: %RAM: 1-PORT%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: lpm_ram_dq

-- ============================================================

-- File Name: Memory.tdf

-- Megafunction Name(s):

-- lpm_ram_dq

--

-- Simulation Library Files(s):

-- lpm

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 8.0 Build 215 05/29/2008 SJ Full Version

-- ************************************************************

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, Altera MegaCore Function License

--Agreement, or other applicable license agreement, including,

--without limitation, that your use is for the sole purpose of

--programming logic devices manufactured by Altera and sold by

--Altera or its authorized distributors. Please refer to the

--applicable agreement for further details.

INCLUDE "lpm_ram_dq.inc";

SUBDESIGN Memory

(

address[7..0] : INPUT;

data[7..0] : INPUT;

inclock : INPUT;

we : INPUT = VCC;

q[7..0] : OUTPUT;

)

VARIABLE

lpm_ram_dq_component : lpm_ram_dq WITH (

LPM_ADDRESS_CONTROL = "REGISTERED",

LPM_INDATA = "REGISTERED",

LPM_OUTDATA = "UNREGISTERED",

LPM_TYPE = "LPM_RAM_DQ",

LPM_WIDTH = 8,

LPM_WIDTHAD = 8

);

BEGIN

q[7..0] = lpm_ram_dq_component.q[7..0];

lpm_ram_dq_component.address[7..0] = address[7..0];

lpm_ram_dq_component.inclock = inclock;

lpm_ram_dq_component.data[7..0] = data[7..0];

lpm_ram_dq_component.we = we;

END;

-- ============================================================

-- CNX file retrieval info

-- ============================================================

-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"

-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"

-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"

-- Retrieval info: PRIVATE: AclrData NUMERIC "0"

-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"

-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"

-- Retrieval info: PRIVATE: Clken NUMERIC "0"

-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"

-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"

-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"

-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "FLEX10K"

-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"

-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"

-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "256"

-- Retrieval info: PRIVATE: MIFfilename STRING ""

-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"

-- Retrieval info: PRIVATE: OutputRegistered NUMERIC "0"

-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"

-- Retrieval info: PRIVATE: RegAdd NUMERIC "1"

-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"

-- Retrieval info: PRIVATE: RegData NUMERIC "1"

-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"

-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"

-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"

-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"

-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"

-- Retrieval info: PRIVATE: WidthData NUMERIC "8"

-- Retrieval info: PRIVATE: rden NUMERIC "0"

-- Retrieval info: CONSTANT: LPM_ADDRESS_CONTROL STRING "REGISTERED"

-- Retrieval info: CONSTANT: LPM_INDATA STRING "REGISTERED"

-- Retrieval info: CONSTANT: LPM_OUTDATA STRING "UNREGISTERED"

-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_RAM_DQ"

-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"

-- Retrieval info: CONSTANT: LPM_WIDTHAD NUMERIC "8"

-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]

-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]

-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock

-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]

-- Retrieval info: USED_PORT: we 0 0 0 0 INPUT VCC we

-- Retrieval info: CONNECT: @address 0 0 8 0 address 0 0 8 0

-- Retrieval info: CONNECT: @we 0 0 0 0 we 0 0 0 0

-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0

-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0

-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0

-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all

-- Retrieval info: GEN_FILE: TYPE_NORMAL Memory.tdf TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL Memory.inc TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL Memory.cmp FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL Memory.bsf TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL Memory_inst.tdf FALSE

-- Retrieval info: LIB_FILE: lpm

Altera_Forum · ‎04-02-2012

--- Quote Start ---

have run into an issue where one of the megafunction-generated VHDL files seems to have an error in it, and I was wondering if anyone on here could help figure out what is causing it. I dont really know much VHDL, so I was wondering if someone could explain to me why this isnt working. Also, I have not edited the VHDL file at all. Any help would be great!

--- Quote End ---

That is not VHDL. I suspect its probably AHDL (Altera's language).

--- Quote Start ---

Error: Text Design File syntax error: Text Design File contains MEMORY where a symbolic name or a number was expected

--- Quote End ---

Perhaps MEMORY is a reserved keyword, and the syntax checker is not smart enough to tell you that. Try changing the name to RAM0.tdf and see what happens.

Cheers,

Dave

Altera_Forum · ‎04-02-2012

Awesome. Thank you!

Altera_Forum · ‎04-02-2012

--- Quote Start ---

Awesome. Thank you!

--- Quote End ---

So that fixed the problem then?