MemWr access failing Quartus Generated PCIe EP on Stratix10MX

[SivaKona]

Hi Syafieq,

We are trying to bring up below design(shown in attached FPGA_noHBM_model.png) on a Stratix10 MX platform.

Quartus Version	Quartus Prime Version 21.2.0.72
PCIe End Point IP	Intel L/H Tile Avalon Memory Mapped for PCI Express
End Point Configuration	Gen3x8 (250MHz)
Mode of End Point	PIO
Enumeration status	EP is getting Enumerated (Device identified on BDF 0b:00.0) on FPGA Platform
Config register Access	PCIe Configuration space is accessible for both Read and Write
Memory Write on BAR0	Transactions are not reaching PCIe EP RXM_BAR0 Application interface (AVMM)
Memory Read on BAR0	Transactions are getting a response data of 0xFFFF_FFFF
MMIO API	Open Source C API (devmem2). devmem2 API is working for BAR0 MemReads of space other devices on the same host

Could you please help us with your inputs on how we can proceed further to debug this issue?

Regards

Siva Kona

[SivaKona]

Hi,

I got to know that there is a known issue with PCIe End Point as described below

"During End Point Enumeration , some Read requests propagate into AVMM Interconnect and hang the interconnect"

Is this issue really True? If Yes , What is the work around ?

Regards

Siva Kona