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i am using the cyclone III Altera with Quartus II and my system specifications are 1 GB RAM, 500 GB Hard disk and Intel dual core processor, i am trying to implement Smwedly model of power converter, the error i am facing is
" error: quartus ii fitter was unsuccessful. 2 errors, 17 warningsInfo: Allocated 151 megabytes of memory during processing Error: Processing ended: Fri July 05 20:31:32 2013 Error: Elapsed time: 00:00:10 error: quartus ii full compilation was unsuccessful. 2 errors, 17 warnings" "
i am seeking guidelines about the error i am facing is that the ram ?
please guide
azhar[/I][/I]
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The actual errors are in the compilation report somewhere above the "2 errors" line.
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Thank you very much for help , i am actually beginner so it is quite confusing for me, i am pasting the Error again following in order to seek help
Info: Found 2 design units, including 1 entities, in source file latchSR.vhd Info: Found design unit 1: latchSR-rtl Info: Found entity 1: latchSR error (10430): VHDL Primary Unit Declaration error at modulatore30aprile.vhd(devil): primary unit "modulatore30aprile" already exists in library "work" Info (10499): VHDL information at azhar.vhd(devil): object "modulatore30aprile" is declared here Info: Found 0 design units, including 0 entities, in source file modulatore30aprile.vhd Info: Found 2 design units, including 1 entities, in source file modulatore30apriletest.vhd Info: Found design unit 1: modulatore30apriletest-architettura1 Info: Found entity 1: modulatore30apriletest Error (10430): VHDL Primary Unit Declaration error at modulatore_finale.vhd(devil): primary unit "modulatore_finale" already exists in library "work"Info: Found 2 design units, including 1 entities, in source file sel_shift.vhd Info: Found design unit 1: sel_shift-scalamento Info: Found entity 1: sel_shift Info: Found 2 design units, including 0 entities, in source file sine_package.vhd Info: Found design unit 1: sine_package Info: Found design unit 2: sine_package-body Info: Found 2 design units, including 1 entities, in source file sine_wave.vhd Info: Found design unit 1: sine_wave-arch1 Info: Found entity 1: sine_wave Info: Found 2 design units, including 1 entities, in source file sinewavecomplex.vhd Info: Found design unit 1: sinewavecomplex-arch11 Info: Found entity 1: sinewavecomplex Info: Found 2 design units, including 1 entities, in source file Vhdl2.vhd Info: Found design unit 1: vhdl2-rtl Info: Found entity 1: vhdl2 error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings Info: Allocated 151 megabytes of memory during processing Error: Processing ended: Mon Jul 08 15:31:40 2013 Error: Elapsed time: 00:00:02 Error: Quartus II Full Compilation was unsuccessful. 2 errors, 0 warnings can you please help?- Mark as New
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HI,
Thank you very much for help , basically i am beginner so it is quite confusing for me, i am pasting the Error again following in order to seek help Info: Found 2 design units, including 1 entities, in source file latchSR.vhd Info: Found design unit 1: latchSR-rtl Info: Found entity 1: latchSR Error (10430): VHDL Primary Unit Declaration error at modulatore30aprile.vhd(devil): primary unit "modulatore30aprile" already exists in library "work" Info (10499): VHDL information at azhar.vhd(devil): object "modulatore30aprile" is declared here Info: Found 0 design units, including 0 entities, in source file modulatore30aprile.vhd Info: Found 2 design units, including 1 entities, in source file modulatore30apriletest.vhd Info: Found design unit 1: modulatore30apriletest-architettura1 Info: Found entity 1: modulatore30apriletest Error (10430): VHDL Primary Unit Declaration error at modulatore_finale.vhd(devil): primary unit "modulatore_finale" already exists in library "work"Info: Found 2 design units, including 1 entities, in source file sel_shift.vhd Info: Found design unit 1: sel_shift-scalamento Info: Found entity 1: sel_shift Info: Found 2 design units, including 0 entities, in source file sine_package.vhd Info: Found design unit 1: sine_package Info: Found design unit 2: sine_package-body Info: Found 2 design units, including 1 entities, in source file sine_wave.vhd Info: Found design unit 1: sine_wave-arch1 Info: Found entity 1: sine_wave Info: Found 2 design units, including 1 entities, in source file sinewavecomplex.vhd Info: Found design unit 1: sinewavecomplex-arch11 Info: Found entity 1: sinewavecomplex Info: Found 2 design units, including 1 entities, in source file Vhdl2.vhd Info: Found design unit 1: vhdl2-rtl Info: Found entity 1: vhdl2 Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings Info: Allocated 151 megabytes of memory during processing Error: Processing ended: Mon Jul 08 15:31:40 2013 Error: Elapsed time: 00:00:02 Error: Quartus II Full Compilation was unsuccessful. 2 errors, 0 warnings could you please help?
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