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I have project which is build on 10M08DCU324 and same i am traying to migrate it to 10M16DCU324. After migration PLL block in my project is not working, just to check whether PLL is working or not i am trying to toggle LED on my board with c2 clock generated from Avalon ALTPLL IP. I am able to toggle LED with inclk0 but it is not working with clock c2. Same project was working as expected with 10M08DCU324. I have checked clock generated on board and it looks ok, also verified reset and it also looks ok. I am not getting what is going wrong, please suggest solution to this problem.
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I see that the question is the same for https://community.intel.com/t5/Intel-Quartus-Prime-Software/Migration-from-10M08DCU324-to-10M16DCU324/m-p/1683989#M86129.
I will let the https://community.intel.com/t5/Intel-Quartus-Prime-Software/Migration-from-10M08DCU324-to-10M16DCU324/m-p/1683989#M86129 taking care of the PLL related setting, while from Quartus tools perspective, do check the below:
Verify Quartus PLL Warning/Info Messages:
After compilation, carefully review the Quartus Messages window for:
PLL warnings
Compensation-related notices
Invalid frequency or out-of-range messages
If Quartus silently reconfigures an invalid setting, it’ll often warn about it.
onstrain the PLL Outputs
Add a clock constraint (create_clock) on c2 in the .sdc file:
create_clock -name c2_clk -period <period_in_ns> [get_ports c2_clk]
This makes sure Quartus respects timing paths using c2 and avoids removing or reconfiguring them unexpectedly.
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Is there further question? If no, we shall close this thread.
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As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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