Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Min Pulse Width 'pcie_refclk' the clock_in of PCIe HIP

SivaKona
Employee
175 Views

Hi 

I have generated a "Intel L/H Tile Avalon Memory Mapped for PCI Express" on Quartus Prime Version 21.2.0.72.

 

I am consistently seeing below violations in all my builds. Am I missing any constraint?

Current Constraints:

create_clock -name {pcie_refclk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {pcie_refclk}]

set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to pcie_refclk

 

 

Status: FAIL
Severity: Medium
Number of violations: 8
Rule Parameters: max_violations = 5000
maximum_pulse_width_slack = 0
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; TMC-20221 - Nodes Failing Minimum Pulse Width Due to Clock Pulse Collapse ;
+---------------------------+------------------+--------------------------------------------------------------+-------------+---------------------------------+--------+
; Minimum Pulse Width Slack ; Type ; Node Name ; Clock ; Worst-Case Operating Conditions ; Waived ;
+---------------------------+------------------+--------------------------------------------------------------+-------------+---------------------------------+--------+
; -81.670 ; High Pulse Width ; pcie_refclk~inputFITTER_INSERTED_FITTER_INSERTED~fpll_c0_div ; pcie_refclk ; 1 Slow vid1 100C Model ; ;
; -81.670 ; Low Pulse Width ; pcie_refclk~inputFITTER_INSERTED_FITTER_INSERTED~fpll_c0_div ; pcie_refclk ; 1 Slow vid1 100C Model ; ;
; -81.670 ; High Pulse Width ; pcie_refclk~inputFITTER_INSERTED_FITTER_INSERTED~fpll_c1_div ; pcie_refclk ; 1 Slow vid1 100C Model ; ;
; -81.670 ; Low Pulse Width ; pcie_refclk~inputFITTER_INSERTED_FITTER_INSERTED~fpll_c1_div ; pcie_refclk ; 1 Slow vid1 100C Model ; ;
; -81.670 ; High Pulse Width ; pcie_refclk~inputFITTER_INSERTED_FITTER_INSERTED~fpll_c2_div ; pcie_refclk ; 1 Slow vid1 100C Model ; ;
; -81.670 ; Low Pulse Width ; pcie_refclk~inputFITTER_INSERTED_FITTER_INSERTED~fpll_c2_div ; pcie_refclk ; 1 Slow vid1 100C Model ; ;
; -81.670 ; High Pulse Width ; pcie_refclk~inputFITTER_INSERTED_FITTER_INSERTED~fpll_c3_div ; pcie_refclk ; 1 Slow vid1 100C Model ; ;
; -81.670 ; Low Pulse Width ; pcie_refclk~inputFITTER_INSERTED_FITTER_INSERTED~fpll_c3_div ; pcie_refclk ; 1 Slow vid1 100C Model ; ;
+---------------------------+------------------+--------------------------------------------------------------+-------------+---------------------------------+--------+

 

Regards

Siva Kona

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1 Solution
SivaKona
Employee
161 Views

I could root cause this issue to signalTap signal.

 

I have added pcie_refclk (input 100MHz clock from IO to PLL of PCIe EP ) to SignalTap while SignalTap Sampling clock was set to pcie_clk(the 250MHz pcie_core_clkout generated by the same PLL)

 

Regards

Siva Kona

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1 Reply
SivaKona
Employee
162 Views

I could root cause this issue to signalTap signal.

 

I have added pcie_refclk (input 100MHz clock from IO to PLL of PCIe EP ) to SignalTap while SignalTap Sampling clock was set to pcie_clk(the 250MHz pcie_core_clkout generated by the same PLL)

 

Regards

Siva Kona

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