Our design is setup in platform designer where we are using an AXI4 master running @ 125 MHz and we are connected to an AXI4Lite slave running at 80 MHz.
Platform designer inserted an AXI bridge, which does protocol crossing and clock domain crossing. So far, so good, but what we see is that when the AXI4 master sets up a burst (4 data words, single address) and the AXI bridge splits up this burst in 4 consecutive writes (also splitting up the addresses) the first 2 writes are handled correctly, but the last 2 are NOT. We don't receive an AWVALID on our addresses, but we do receive WVALIDs on the data...
Is this a bug? Or normal behavior? Could anybody please clarify this for me?
What I see is that the bridge continues transferring data when either the address or data channel is acknowledged... Is that good behavior?
Thank you in advance.
The problem is resolved. At least there is a workaround: by NOT writing bursts to this bridge, but single writes, all goes well.
Since our receiving end is AXI4lite we don't support bursts anyway. Strange that it sometimes does work en sometimes it doesn't but it's what it is.