ModelSim Error

[MR23]

I have downloaded Quartus 20.1 version along with Modelsim and device. While I was trying to create University program VWF, I was getting the above error. It

[MR23]

Following another community response, I tried this:  

"It's a bug. In the Simulation Waveform Editor, choose Simulation Settings|Simulation Options and delete -novopt following vsim in the Model Script (and save the changes)."

Now I am getting another error:

This is the code for my 2x1 multiplexer:

module mux21(out, A, B, Sel);
input Sel, A, B;
output out;
assign out = Sel?A:B;
endmodule

Any suggestion?

Thanks.

[MR23]

I tried the above verilog code one more time without changing anything else. Now I am getting a different error. I desperately need some help?

[MR23]

Mr. Moderator, 

I am having the exact same error. Please find below the code I used this time. One thing, I want to mention here is that I have been using Quartus Prime Standard edition for last 4/5 years ( Got the license from Altera as a donation). I used only the verilog code to generate the VWF form without any issue until recently. It's really frustrating......

// define a module for the design
module mux21(in1, in2, select, out);

// define input port
input in1, in2, select;

// define the output port
output out;

// assign one of the inputs to the output based upon select line input
assign out = select ? in2 : in1;
endmodule

module test;
reg in1, in2, select;
wire out;

// design under test
mux21 mux(.in1(in1), .in2(in2),
.select(select), .out(out));

// list the input to the design
initial begin in1=1'b0;in2=1'b0;select=1'b0;
#2 in1=1'b1;
#2 select=1'b1;
#2 in2=1'b1;
#2 $stop();
end

// monitor the output whenever any of the input changes
initial begin $monitor("time: =%0b","input1 =%0b","input2 =%0b","select =%0b", "output =%0b", $time, in1,in2,select,out);
end
endmodule

[SyafieqS]

To seem there Testbench instantiation issue, which is missing all the port A,B,Sel,Out.

Can you verify your tb?

[MR23]

I don't have any testbench code for this circuit? Do I need one??

[SyafieqS]

Yes you have to have tb whenever doing a simulation to verify the functionality of your circuit.

[FvM]

Hi,
with university program VWF simulator, the testbench is generated automatically, you can write a simulation waveform with the graphical vwf editor and start the generation process. Or generate it automatically, as described above. It's intended as a replacement for the old built-in Quartus simulator but, as far as I understand, never got a full professional product status. As the "university program" context suggests, it's delivered as is and is somehow experimental.

Having said this, I must confess that I don't know if the vwf simulator flow has issues with recent Quartus + Modelsim versions. It worked for me e.g. with Quartus 13, but I prefer regular Modelsim/Questasim testbenches and never tried vfw simulation method with newer versions.

[MR23]

As I mentioned earlier, I do have access to the Quartus Prime 16 version. It worked for me until last summer. Now it's giving me the same error as Quartus Lite. What would you suggest then?  Quartus 13 is not available anymore. 

[SyafieqS]

I am sending something to your email.

[MR23]

Hi Syafieq,

As I downloaded Quartus II 13.0 web edition, I am able to create the webform. However, I have a new issue now. I have created a majority circuit ( output will be high if any two of three inputs are high).

This is what I am getting in response to the above input file. 

If you look into the read only output file, you will see that it's remembering a previously created circuit (32bit adder). I tried all possible way to close that earlier project. Still it remembers that.  Any suggestion?

[MR23]

If I am using a different folder, it works just fine.