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Altera_Forum
Honored Contributor I
1,317 Views

ModelSim Intel FPGA Starter edition 10.5b fails to simulate due to mem alloc fail

Just fired up ModelSim FPGA Starter edition 10.5b and tried to simulate the simplest of models to get a feel for the tool. The testbench contains a file reader pushing test vectors into a DUT stub. Goes nowhere fast. 

 

Working on a Windows 10 PC, with an i7, 16GB memory, 200GB of swap, no other tools running, so there is plenty of memory available, but vsim provides this log: 

 

vsim work.add_tb(behavior)# vsim work.add_tb(behavior) # Start time: 08:01:46 on Mar 23,2018# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading ieee.std_logic_textio(body)# Loading ieee.numeric_std(body)# Loading work.add_tb(behavior)# Loading work.test_vector_reader(behavior)# ** Fatal: (vsim-4) ****** Memory allocation failure. *****# Attempting to allocate 2147483664 bytes# Please check your system for available memory and swap space.# ** Fatal: (vsim-4) ****** Memory allocation failure. *****# Attempting to allocate 2147483664 bytes# Please check your system for available memory and swap space.# ** Fatal: (vsim-4) ****** Memory allocation failure. *****# Attempting to allocate 2147483648 bytes# Please check your system for available memory and swap space.# ** Fatal: (vsim-4) ****** Memory allocation failure. *****# Attempting to allocate 2147483648 bytes# Please check your system for available memory and swap space.# ** Fatal: (SIGSEGV) Bad handle or reference.# Time: 0 ps Iteration: 0 Process: /add_tb/U1/file_io File: C:/Users/tomtz/Documents/dev/posit-qa/hw/vhdl/test_vector_reader.vhdl# FATAL ERROR while loading design# Error loading design
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7 Replies
Altera_Forum
Honored Contributor I
165 Views

modelsim as supplied in starter edition is simply a 32bit application, so you're limited to 2GB of ram. 

But using 2GB is a bit of a challenge - how have you managed it? are you trying to load the entire contents of a DDR?  

 

Why not give us a hint as to what you're trying to do, and maybe we can help?
Altera_Forum
Honored Contributor I
165 Views

 

--- Quote Start ---  

modelsim as supplied in starter edition is simply a 32bit application, so you're limited to 2GB of ram. 

But using 2GB is a bit of a challenge - how have you managed it? are you trying to load the entire contents of a DDR?  

 

Why not give us a hint as to what you're trying to do, and maybe we can help? 

--- Quote End ---  

 

 

As indicated in the original request: I am trying to simulate a testbench that consists of a test vector file reader pushing into an empty DUT entity. The simulation fails with these memory allocation errors. The model will not need 2GB of memory so run, so something else is failing.
Altera_Forum
Honored Contributor I
165 Views

Without posting some code to help us, I can only conclude there is something wrong with your testbench. Modelsim doesnt use much memory usually. 

Is the file you're trying to read large? what are you reading the file to? Given the failures are occuring during elaboration time, are you reading this file to a large signal? Signals take a lot of ram, so even a 128Mb memory simulated as a signal could eat more than 2GB of ram (maybe even smaller). 

 

Without code, these are only guesses. Your assertion that "The model will not need 2GB of memory so run, so something else is failing." is likely to be wrong. Modelsim clearly needs more than 2GB to run this test.
Altera_Forum
Honored Contributor I
165 Views

can you post test_vector_reader.vhdl?

Altera_Forum
Honored Contributor I
165 Views

LIBRARY IEEE,STD; 

USE IEEE.STD_LOGIC_1164.ALL; 

USE IEEE.STD_LOGIC_TEXTIO.ALL; 

USE STD.TEXTIO.ALL; 

 

ENTITY test_vector_reader IS 

GENERIC (NBITS : integer); 

PORT ( 

op1 : out std_logic_vector(NBITS-1 downto 0); 

op2 : out std_logic_vector(NBITS-1 downto 0); 

ref : in std_logic_vector(NBITS-1 downto 0)); 

END test_vector_reader; 

 

ARCHITECTURE behavior OF test_vector_reader IS 

BEGIN 

file_io: PROCESS IS 

FILE in_file : TEXT OPEN READ_MODE IS "addition_posit_5_0.vnv"; 

FILE out_file : TEXT OPEN WRITE_MODE IS "vnv_results"; 

VARIABLE out_line : LINE; 

VARIABLE in_line : LINE; 

 

VARIABLE nbits : INTEGER; 

VARIABLE es : INTEGER; 

VARIABLE testCase : INTEGER; 

VARIABLE a,b,c : STD_LOGIC_VECTOR(NBITS-1 downto 0); 

VARIABLE result : STD_LOGIC_VECTOR(NBITS-1 downto 0); 

BEGIN 

-- read and report the posit configuration 

READLINE(in_file, in_line); 

READ(in_line, nbits); 

READ(in_line, es); 

-- construct an output message to the console 

WRITE(out_line, string'("posit<")); 

WRITE(out_line, nbits); 

WRITE(out_line, string'(",")); 

WRITE(out_line, es); 

WRITE(out_line, string'(">")); 

WRITELINE(OUTPUT, out_line); 

 

-- read the test vector elements 

WHILE NOT ENDFILE(in_file) LOOP 

READLINE(in_file, in_line); 

READ(in_line, testCase); 

READ(in_line, a); 

READ(in_line, b); 

READ(in_line, c); 

 

-- construct an output message 

WRITE(out_line, a); 

WRITE(out_line, string'(" + ")); 

WRITE(out_line, b); 

WRITE(out_line, string'(" = ")); 

WRITE(out_line, c); 

WRITELINE(OUTPUT, out_line); 

 

-- schedule signal transactions 

op1 <= a; 

op2 <= b; 

WAIT; 

 

 

WRITE(out_line, result); 

WRITELINE(out_file, out_line); 

END LOOP; 

ASSERT FALSE REPORT "Simulation done" SEVERITY NOTE; 

WAIT; --allows the simulation to halt! 

END PROCESS file_io; 

 

END ARCHITECTURE behavior;
Altera_Forum
Honored Contributor I
165 Views

here is a test vector file: everything after the | is for human inspection, it isn't used by the testbench. 

 

5 0 posit<5,0> 

1 00000 00000 00000 | 0 + 0 == 0 

2 00000 00001 00001 | 0 + 0.125 == 0.125 

3 00000 00010 00010 | 0 + 0.25 == 0.25 

4 00000 00011 00011 | 0 + 0.375 == 0.375 

5 00000 00100 00100 | 0 + 0.5 == 0.5 

6 00000 00101 00101 | 0 + 0.625 == 0.625 

7 00000 00110 00110 | 0 + 0.75 == 0.75 

8 00000 00111 00111 | 0 + 0.875 == 0.875 

9 00000 01000 01000 | 0 + 1 == 1 

10 00000 01001 01001 | 0 + 1.25 == 1.25 

11 00000 01010 01010 | 0 + 1.5 == 1.5 

12 00000 01011 01011 | 0 + 1.75 == 1.75 

13 00000 01100 01100 | 0 + 2 == 2 

14 00000 01101 01101 | 0 + 3 == 3 

15 00000 01110 01110 | 0 + 4 == 4 

16 00000 01111 01111 | 0 + 8 == 8 

17 00000 10000 10000 | 0 + NaR == NaR 

18 00000 10001 10001 | 0 + -8 == -8 

19 00000 10010 10010 | 0 + -4 == -4 

20 00000 10011 10011 | 0 + -3 == -3 

21 00000 10100 10100 | 0 + -2 == -2 

22 00000 10101 10101 | 0 + -1.75 == -1.75 

23 00000 10110 10110 | 0 + -1.5 == -1.5 

24 00000 10111 10111 | 0 + -1.25 == -1.25 

25 00000 11000 11000 | 0 + -1 == -1 

26 00000 11001 11001 | 0 + -0.875 == -0.875 

27 00000 11010 11010 | 0 + -0.75 == -0.75 

28 00000 11011 11011 | 0 + -0.625 == -0.625 

29 00000 11100 11100 | 0 + -0.5 == -0.5 

30 00000 11101 11101 | 0 + -0.375 == -0.375 

31 00000 11110 11110 | 0 + -0.25 == -0.25 

32 00000 11111 11111 | 0 + -0.125 == -0.125
Altera_Forum
Honored Contributor I
165 Views

How is test_vector reader instantiated? Have you accidently set NBITs really high? 

 

Have you tried debugging to find whats causing the issue? you can often find it by commenting out code until the problem goes away, or commenting it all out and adding it bit by bit until the problem happens again. 

 

Couple comments on the code though:  

What does ref do? 

Why do you have 2 waits in the process? The process will halt forever at the first one.
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