Modelsim-Altera do file paths

[ZKhan1]

HI ,

I have a design in which i have placed all ip that i have used in separate folders like for pll i have put the generated files in altera_pll , for dpram in altera_dpram .

I can compile the design in Quartus Prime ver 18.1 , but when try to run simulation the modelsim complaines about "library found " etc .

I tried to edit the .do file , but it is over written .

Is there a way to run the simulation with this setup ?

Regards , Ahmed 

[RichardTanSY_Intel]

Modelsim Intel FPGA Edition support NativeLink (standard/lite version only) and scripted simulation flow. Which setup that you are refer to?

[RichardTanSY_Intel]

You may checkout Quick Start below for scripted simulation flow and cross check with your current flow.

https://www.intel.com/content/www/us/en/docs/programmable/683305/19-4/simulation-quick-start.html

[ZKhan1]

These are the  Modelsim errors :

vcom -93 -work work {C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pas_rs_hssl_mk2_fw/hssl_mk2_hbi_interface.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 13:27:30 on May 31,2022
# vcom -reportprogress 300 -93 -work work C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pas_rs_hssl_mk2_fw/hssl_mk2_hbi_interface.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# ** Error: C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pas_rs_hssl_mk2_fw/hssl_mk2_hbi_interface.vhd(45): (vcom-1598) Library "lib_top_pas_rs_hssl_mk2_fw" not found.
# ** Error: C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pas_rs_hssl_mk2_fw/hssl_mk2_hbi_interface.vhd(46): (vcom-1136) Unknown identifier "lib_top_pas_rs_hssl_mk2_fw".
# ** Error: C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pas_rs_hssl_mk2_fw/hssl_mk2_hbi_interface.vhd(48): VHDL Compiler exiting
# End time: 13:27:30 on May 31,2022, Elapsed time: 0:00:00
# Errors: 3, Warnings: 0
# ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vcom failed.
# Error in macro ./top_pas_rs_hssl_mk2_fw_run_msim_rtl_vhdl.do line 14
# C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vcom failed.
# while executing
# "vcom -93 -work work {C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pa

[ZKhan1]

And this is how my user libraries are define in vhdl top file :

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

LIBRARY altera_ip;
USE altera_ip.ALL;

LIBRARY cyclone10lp;
USE cyclone10lp.ALL;
--LIBRARY cyclone10lp_components;
USE cyclone10lp_components.ALL;

LIBRARY lib_top_pas_rs_hssl_mk2_fw;
USE lib_top_pas_rs_hssl_mk2_fw.ALL;

LIBRARY lib_reset_crtl;
USE lib_reset_crtl.ALL;

LIBRARY lib_app_hbi;
USE lib_app_hbi.ALL;

[RichardTanSY_Intel]

As shown in the error message, the library "lib_top_pas_rs_hssl_mk2_fw" is not found.

I see that you are using quartus lite, could you try to run the Nativelink Simulation ?

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/quartus/simulation-nativelink-howto.html

[ZKhan1]

All the relevant Nativelink settings are in place , this is after Modelsim is invoked and the testbench has been correctly setup.

I have another version of this same project with successful simulation , but all the altera ip vhd and qip files are in root directory of the project .

So back to my previous question , what cantt modelsim pick up the files from their folders ? 

[RichardTanSY_Intel]

After you move the files, have you tell Quartus to compile the project again with the new files directory?

Nativelink is an automated simulation flow to generate simulation scripts, compile simulation libraries, and auto launch your simulator following design compilation.

So, it is normal to see that your .do file has been written over every time you run Nativelink.

[RichardTanSY_Intel]

My guess is that modelsim is not directed to the correct file directory.

Check your .do file and see if it is correct. Since you have a success simulation case, you should be able to compare between the .do file and see where goes wrong.

[RichardTanSY_Intel]

I have yet to receive any response from you to the previous question/reply/answer that I have provided but I believed that I have answered your question. 

With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos and select the best solution. 

[ZKhan1]

Please read my initial post , in the working project all the altera ips .vhd and .qip files are in root directory of the project .

But what i want is a separate folder for each ip and the modelsim be able to read from those folders each of the .vhd and .qip files .