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Altera_Forum
Honored Contributor I
1,302 Views

Modelsim: Unresolved defparam reference to somewhere

In Quartus ii schematic diagram, i've generated an lpm_ff. Then i've converted the design to a .v file. when i want to use this flip-flop in a module, it compiles with no problems but when i want to simulate it with modelsim i receive this error for all defparams in the code in the : 

 

 

Error: (vsim-10000) C:/.../lpm_ff_8.v(30): Unresolved defparam reference to 'LPM_WIDTH' in lpm_instance.LPM_WIDTH. 

 

 

 

 

 

Here is the code of `ff` that Quartus generated: 

 

 

module lpm_ff_8(clock,sload,data,q); input clock; input sload; input data; output q; lpm_ff lpm_instance(.clock(clock),.sload(sload),.data(data),.q(q)); defparam lpm_instance.LPM_AVALUE = 1; defparam lpm_instance.LPM_FFTYPE = "DFF"; defparam lpm_instance.LPM_SVALUE = 0; defparam lpmi_nstance.LPM_WIDTH = 16; endmodule  

 

And the module i use this flip-flop in it: 

module test(input a, clk, output reg q); lpm_ff_8 regg(.data(a), .clock(clk), .q(q)); endmodule module testTB(); reg a; reg clk; wire q; test t(a, clk, q); initial begin # 15 clk = 1; end endmodule  

 

I also add lpm_ver library when i want to simulate. So can you help me to find what's wrong with this code?
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1 Reply
Altera_Forum
Honored Contributor I
118 Views

Hi, 

1. Here is Typo mistake, 

Defparam lpmi_nstance.LPM_WIDTH = 16; ---> lpm_instance.LPM_WIDTH  

2. Missed port sload while instantiation & declare all inputs & outputs before use it & then instantiate, 

lpm_ff_8 regg(.data(a), .clock(clk), .q(q)); 

 

note: unfortunately handled old thread while handling thread 59117 

 

Best Regards 

Vikas Jathar  

(This message was posted on behalf of Intel Corporation)
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