Modelsim Warning Hold Violation

Altera_Forum · ‎03-29-2015

I have a design that full compile without timing errors in TimeQuest but when I do gate level simulation I get:

# Expected := 0.157 ns; Observed := 0.116 ns; At : 7740.295 ns# Time: 7740295 ps Iteration: 1 Instance: /schematic_tb/uut/my_signal..# ** Warning: */DFFEAS HOLD High VIOLATION ON DATAIN WITH RESPECT TO CLK;

a lot of times at different time

Why? Should I do something? With TimeQuest I haven't hold violations.

Thanks

PS: Quartus 13.0 SP1, ModelSim Altera Starter 10.1d, Cyclone IV E (DE0-Nano)

Altera_Forum · ‎03-29-2015

Do you have time specs for these registers? Are they async latches?

Altera_Forum · ‎03-29-2015

I just solved. With Design Assistant I found reset signal that are async and caused this problem during simulation that was not catched by TimeQuest.

Thank you anyway