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Modelsim is not working with PCIe IP generated VHDL

K_T
Beginner
358 Views

I encounter problems for Cyclone V development.

My design consist of 2 PCIe HIPs and some our logics.

 I am useing "Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"

I simulate our design with the Modelsim Intel FPGA Sterter Edition included QuartusII, and errors occur on the Modelsim as follows;

 

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...

 

# Loading bar0_arm_s0_rsp_width_adapter.altera_merlin_burst_uncompressor

# Loading altera_avalon_ecc_enc.altera_avalon_ecc_enc(rtl)

# Loading altera_avalon_ecc_enc.PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_enc_altera_avalon_ecc_enc

# Loading altera_avalon_ecc_dec.altera_avalon_ecc_dec(rtl)

# Loading altera_avalon_ecc_dec.PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec# ** Error (suppressible): (vsim-10000) [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v(113): Unresolved defparam reference to 'error_bit_decoder' in error_bit_decoder.lpm_deco

#   Time: 0 ps Iteration: 0 Instance: /top_vhd_tst/i1/u_pcie_x86_if/u0_PCIE_x86/mm_interconnect_0/bar0_x86_s0_agent_rdata_fifo/ecc_on/ecc_dec/genblk1/dec_mod[0]/genblk1/ecc_dec/altera_avalon_ecc_dec File: [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v

# ** Error (suppressible): (vsim-10000) [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v(114): Unresolved defparam reference to 'error_bit_decoder' in error_bit_decoder.lpm_width.

#   Time: 0 ps Iteration: 0 Instance: /top_vhd_tst/i1/u_pcie_x86_if/u0_PCIE_x86/mm_interconnect_0/bar0_x86_s0_agent_rdata_fifo/ecc_on/ecc_dec/genblk1/dec_mod[0]/genblk1/ecc_dec/altera_avalon_ecc_dec File: [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v

# ** Error (suppressible): (vsim-10000) [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v(115): Unresolved defparam reference to 'error_bit_decoder' in error_bit_decoder.lpm_type.

#   Time: 0 ps Iteration: 0 Instance: /top_vhd_tst/i1/u_pcie_x86_if/u0_PCIE_x86/mm_interconnect_0/bar0_x86_s0_agent_rdata_fifo/ecc_on/ecc_dec/genblk1/dec_mod[0]/genblk1/ecc_dec/altera_avalon_ecc_dec File: [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v

# ** Error (suppressible): (vsim-10000) [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v(113): Unresolved defparam reference to 'error_bit_decoder' in error_bit_decoder.lpm_decodes.

#   Time: 0 ps Iteration: 0 Instance: /top_vhd_tst/i1/u_pcie_x86_if/u0_PCIE_x86/mm_interconnect_0/bar0_x86_s0_agent_rdata_fifo/ecc_on/ecc_dec/genblk1/dec_mod[1]/genblk1/ecc_dec/altera_avalon_ecc_dec File: [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v

# ** Error (suppressible): (vsim-10000) [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v(114): Unresolved defparam reference to 'error_bit_decoder' in error_bit_decoder.lpm_width.

#   Time: 0 ps Iteration: 0 Instance: /top_vhd_tst/i1/u_pcie_x86_if/u0_PCIE_x86/mm_interconnect_0/bar0_x86_s0_agent_rdata_fifo/ecc_on/ecc_dec/genblk1/dec_mod[1]/genblk1/ecc_dec/altera_avalon_ecc_dec File: [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v

# ** Error (suppressible): (vsim-10000) [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v(115): Unresolved defparam reference to 'error_bit_decoder' in error_bit_decoder.lpm_type.

#   Time: 0 ps Iteration: 0 Instance: /top_vhd_tst/i1/u_pcie_x86_if/u0_PCIE_x86/mm_interconnect_0/bar0_x86_s0_agent_rdata_fifo/ecc_on/ecc_dec/genblk1/dec_mod[1]/genblk1/ecc_dec/altera_avalon_ecc_dec File: [SOURCE_DIR]/IP/PCIE_x86/simulation/submodules/PCIE_x86_mm_interconnect_0_bar0_x86_s0_agent_rdata_fifo_altera_avalon_ecc_dec_altera_avalon_ecc_dec.v

...

--------

 

 

I checked error number(vsim-10000), found the page follows;

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

 

I fixed "do" file as instructed on this page, but same error occured again.

 

I generated simulation file of Qsys with VHDL, selected VHLD on format for output netlist option on QuartusII.

If I change these selection to Verilog, the errors do not occur.

0 Kudos
3 Replies
SengKok_L_Intel
Moderator
147 Views

Hi,

 

For the PCIe Cyclone V IP user guide, it is suggested to generate the example design/simulation model by using the Verilog. Therefore, the VHDL may not work in this case.

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avmm.pdf

 

Regards -SK

K_T
Beginner
147 Views

​Hi,

OK, I'll try to simulate design using Verilog.

Best Regards

SengKok_L_Intel
Moderator
147 Views

Thanks

Reply