I want to synthesize soft CPU IP by itself and evaluate resources.
I created a TOP wrapper to implement a CPU module.
However, when I look at the compilation result, I can't find the CPU module I implemented.
When I check the Registers Removed During Synthesis in the compile log, I see a lot of registers.
I tried the option to disable optimization, but it didn't work.
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
Is there any other way to prevent the module from being removed by compilation optimization?
Which Quartus version are you using? The latest 21.3 has a new report called 'Hierarchies Optimized Away During Sweep" that includes the details on what is optimized away alongside with the reasons.
Yes, there is synthesis Quartus attribute so called noprune/preserve the register from being removed.
Is your design or this soft CPU you mention (Nios?) not connected to any I/O? That is a lot getting optimized away. What does the report mentioned indicate?
If you're not connected to I/O pins, add Virtual Pin assignments in the Assignments Editor to prevent unconnected logic from getting optimized away.
CPU was released by the 3rd vendor.
I created a Top wrapper that outputs the IO of the CPU Top module to the FPGA pin.
However, since the number of CPU IOs is large for FPGA pins, some inputs are input from registers.