Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Module removal by compilation optimization

mappy5
Beginner
1,975 Views

I want to synthesize soft CPU IP by itself and evaluate resources.

I created a TOP wrapper to implement a CPU module.
However, when I look at the compilation result, I can't find the CPU module I implemented.
When I check the Registers Removed During Synthesis in the compile log, I see a lot of registers.

I tried the option to disable optimization, but it didn't work.
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF

Is there any other way to prevent the module from being removed by compilation optimization?

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8 Replies
skyjuice
Employee
1,965 Views

Which Quartus version are you using? The latest 21.3 has a new report called 'Hierarchies Optimized Away During Sweep" that includes the details on what is optimized away alongside with the reasons.

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mappy5
Beginner
1,947 Views

hi skyjuice 

Quartus version :20.3 build 158 pro edition 

I will install 21.3 and try it. 

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SyafieqS
Employee
1,955 Views
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mappy5
Beginner
1,947 Views

Hi

There are 3147400 deleted registers.

Do I need to add a pragma to Verilog for everything?

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sstrell
Honored Contributor III
1,946 Views

Is your design or this soft CPU you mention (Nios?) not connected to any I/O?  That is a lot getting optimized away.  What does the report mentioned indicate?

If you're not connected to I/O pins, add Virtual Pin assignments in the Assignments Editor to prevent unconnected logic from getting optimized away.

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mappy5
Beginner
1,932 Views

CPU was released by the 3rd vendor.

I created a Top wrapper that outputs the IO of the CPU Top module to the FPGA pin.

However, since the number of CPU IOs is large for FPGA pins, some inputs are input from registers.

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sstrell
Honored Contributor III
1,879 Views

So can you answer the question I asked?  What exactly does the report indicate is getting optimized away?  And have you tried adding virtual pin assignments?

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SyafieqS
Employee
1,786 Views

Hi,


Are you able to implement the synthesis attribute to avoid the register from being optimized?


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