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Valued Contributor III
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Mutiplexer giving high impedance while connected serially to a D-Flip Flop

Hi guys, 

 

I am very much new to verilog and I have been trying to replicate an LUT-FF pair with a multiplexer to select the output from either directly from the LUT or from the D-FF. When I tried connecting all three modules, I found that the LUT output is coming as 'Z'. I have individually tested all three modules (LUT, D-FF and 2x1 MUX) and they are working fine. I think something might be wrong with my test bench but I am not able to find out the issue. 

Please find the code below. Any kind of help is much appreciated. 

 

module test_bench(); 

wire MuxOut; 

reg [15:0] In; 

reg [3:0] sel; 

reg clk,reset,switch; 

logic_pair LUTFF(.inp(sel),.lut(In),.sel(switch),.clk(clk),.reset(reset),.out(MuxOut)); 

 

 

initial begin 

// Initiliase Input Stimulus 

 

 

 

 

clk = 1'b0; 

reset=1'b1; 

switch=1'b0; 

In = 16'b1100_0011_1011_0101;  

sel=4'b0000; 

 

 

forever# 100 clk=!clk; 

end 

always @(posedge clk) 

begin # 5; 

 

 

sel=4'b0000; 

reset=1'b0; 

switch=0;# 10; 

sel=4'b0001; 

switch=0; 

reset=1'b0;# 10; 

 

 

sel=4'b0010; 

switch=0; 

reset=1'b0;# 10; 

reset=1'b1; 

switch=1; 

sel=4'b1000; 

sel=4'b1000; 

sel=4'b0100;# 400 $finish; 

end 

initial begin 

$dumpfile("x.vcd"); 

 

 

$dumpvars(0,test_bench); 

$timeformat(-9, 1, " ns", 6); 

$monitor("At t=%t sel=%b In=%b_%b MuxOut=%b reset=%b switch=%b",$time,sel,In[15:8],In[7:0],MuxOut,reset,switch); 

end 

 

 

//Stimulus 

 

 

 

 

 

 

endmodule 

 

module logic_pair(inp,lut,sel,clk,reset,out); 

input [15:0] lut; 

input [3:0] inp; 

input sel; 

input clk,reset; 

output out; 

wire out_lut,out_ff; 

 

 

LU L1(.in1(lut), .in2(inp), .out2(out_lut)); 

syn_D_FF FF1(.data_in(out_lut),.clk(clk),.reset(reset),.data_out(out_ff)); 

MUX_FF_LUT FF_LUT(.lut(out_lut),.ff(out_ff),.sel(sel),.out(out)); 

 

 

endmodule 

 

 

module LU(in1, in2, out2); 

input wire [15:0] in1; 

input wire [3:0] in2; 

output reg out2; 

always@(in2 or in1) 

case (in2) 

4'b0000: out2 <= in1[0]; 

4'b0001: out2 <= in1[1]; 

4'b0010: out2 <= in1[2]; 

4'b0011: out2 <= in1[3]; 

4'b0100: out2 <= in1[4]; 

4'b0101: out2 <= in1[5]; 

4'b0110: out2 <= in1[6]; 

4'b0111: out2 <= in1[7]; 

4'b1000: out2 <= in1[8]; 

4'b1001: out2 <= in1[9]; 

4'b1010: out2 <= in1[10]; 

4'b1011: out2 <= in1[11]; 

4'b1100: out2 <= in1[12]; 

4'b1101: out2 <= in1[13]; 

4'b1110: out2 <= in1[14]; 

4'b1111: out2 <= in1[15]; 

endcase 

endmodule 

 

module MUX_FF_LUT(lut,ff,sel,out); 

input lut,ff,sel; 

output reg out; 

always@(sel) 

begin 

case (sel) 

1'b0: out <= lut; 

1'b1: out <= ff; 

//default : out <= lut; 

endcase 

end 

endmodule 

 

module syn_D_FF(data_in,data_out,clk,reset);  

input data_in; 

input clk,reset; 

 

 

output reg data_out; 

 

 

always@(posedge clk or negedge reset) 

begin 

if(reset) 

data_out<=1'b0; 

else 

data_out<=data_in; end 

 

 

endmodule
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3 Replies
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Valued Contributor III
7 Views

Hi! 

 

The "always@(posedge clk or negedge reset)" statement should be "always@(posedge clk or posedge reset)" as you trigger on a rising reset input. 

 

And you should use a complete sensitivity list (all signals at the right side of "=") at: 

"always@(sel)". Or the simple way: "always @*" 

 

Use "=" instead of "<=" in combinatorial blocks ("always @*"). 

 

With these changes your output should be 1'b0 or 1'b1 instead of x.
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Highlighted
Valued Contributor III
7 Views

 

--- Quote Start ---  

Hi! 

 

The "always@(posedge clk or negedge reset)" statement should be "always@(posedge clk or posedge reset)" as you trigger on a rising reset input. 

 

And you should use a complete sensitivity list (all signals at the right side of "=") at: 

"always@(sel)". Or the simple way: "always @*" 

 

Use "=" instead of "<=" in combinatorial blocks ("always @*"). 

 

With these changes your output should be 1'b0 or 1'b1 instead of x. 

--- Quote End ---  

 

 

 

Thanks a lot!! Now the code is working perfectly
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Highlighted
Valued Contributor III
7 Views

@DUESTERBERG Thanks a lot!!! Now the code is working perfectly

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