My M9K blocks get always synthesized away!

[AAlas3]

Hey,

I am using MegaFunction to instantiate M9K SRAM blocks in my design and the Quartus 17.0 software always syntheszies away my M9K blocks, my design consists of Reset signal and the memory blocks driving outputs

Please help this issue is driving me crazy

My board is DE2-115

[ak6dn]

Well, if Quartus detects that your memory is never written and holds a constant data pattern it can optimize it away and replace it with simple logic.

Quartus is pretty smart about optimizing away logic it detects as not being used (eg, generated logic that does not drive any other logic can be eliminated).

[Kenny_Tan]

Quartus will show the reason why those ram was optimized away. Can you check in your Processing -> Compilation report. Look into all the details over there.

[AAlas3]

What I did is building a module that generates Sine wave and save enough samples of this wave in M9K blocks then I connect M9K blocks to VGA driver block so that I can see output on the screen but the fitter keeps destroying the entire memory and I don't know why

[ak6dn]

First, does the design run in simulation? You describe what the design is supposed to do, but does it behave that way in simulation?

Second, look in your design .map.rpt file, couple of sections:

  16. Registers Removed During Synthesis

 17. Removed Registers Triggering Further Register Optimizations

will tell you which register blocks have been removed, and give a reason why.

[AAlas3]

The design runs in simulation as expected and to make sure more I made a hardware test where I used the VGA chip as a DAC and saw the sine on my scope and everything works perfectly but the problem arises after connecting the M9K blocks to internal

circuity to move on on my project

I will check the rest now

[AAlas3]

90% of removals due to stuck pins!

[Kenny_Tan]

Do you mean stuck pin to GND or VCC? If yes, you should be able to correct it.

[AAlas3]

Yes stuck either to GND or VCC, Thanks a lot my friend you give me what I need to understand this behavior, from my code if statements don't cover everything related to M9K so these uncovered portions of my code synthesized to GND or VCC in RTL when I set a complete description to M9K everything is working as I designed it, but I have another question here, What is the difference between Logic Low (0) and GND in RTL? it seems the software differentiates between them

[Kenny_Tan]

Logic Low (0) and GND  should be the same. Can you look into the rtl viewer to see if they got different?

[AAlas3]

If anything connected to GND it will be synthesized away and if it is just a Logic Low it won't be synthesized away that's what I noticed, forgive me but I think they should be the same I am just telling you what I noticed

[Kenny_Tan]

Did you check on the technology map viewer as well? If it is synthesized away, those logic will be gone there.

[AAlas3]

Yes, all of them are gone in Technology Map Viewer, Quartus destroyed a great portion of the system

[ak6dn]

GND and logic low behave identically. So do VCC and logic high.

Quartus did not destroy anything. It optimized out logic that could be replaced by a constant value. You most likely need to check your design.

There is an outside chance you have found a bug in Quartus, but you are going to need substantial proof to claim this is true.

[AAlas3]

​it appears that the problem was due to incomplete Verilog description, I just added a couple of "If statements" and everything worked fine