NIOSデバッグについて

[YSuzu21]

NIOS-Eclipse is used for debugging.

The problem occurs when running The problem occurs when running Debug as → Nios II Hardware.

When a CLK such as NIOS, JTAGUART, or PIO is directly input at 50MHz, the

No problem.

However, using PLLs, we can generate 50MHz to 40MHz and

An error occurs when inputting to the CLK of NIOS, JTAGUART, PIO, etc.

The PLL is not reset.

No problem if you don't use the PLL.

The problem occurs when using PLL.

The reason for generating 40MHz is that the operating frequency of the RSU with Dualboot is

This is because the datasheet said 40MHz (max).

Is the PLL a problem?

Is the 40 MHz frequency the problem?

You can run Nios II Hardware at 50MHz without any problem, but

In order to do Dualboot, it is necessary to make it 40MHz and I am having trouble with debugging.

Please let me know.

[Isaac_V_Intel]

Hello Yasuyuki,

My first question for you is which version of NIOS are you using?

Regarding the ELF process failed, can you make sure that the NIOS debug reset output back to nios reset input QSYS?

See Figure 2 in the following link[1].

[1] https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_nios2_flash_programmer.pdf

[YSuzu21]

Thank you for your reply.