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Altera_Forum
Honored Contributor I
807 Views

Nallatech 385A Quartus Fitter Failed

I could use some help compiling a fairly simple, Intel authored OpenCL kernel on a Nallatech 385A (GX1150). After about four hours after running the following command (or with the default board p385a_sch_ax115 and various other attempts) 

 

aoc -v -report sha1.cl -DALTERA_CL -DFPGA -board=p385a_min_ax115  

 

we get the following output: 

 

aoc: Environment checks are completed successfully. aoc: If necessary for the compile, your BAK files will be cached here: /var/tmp/aocl/gm78 You are now compiling the full flow!! aoc: Selected target board p385a_min_ax115 aoc: Running OpenCL parser.... aoc: OpenCL parser completed successfully. aoc: Optimizing and doing static analysis of code... aoc: Linking with IP library ... Checking if memory usage is larger than 100% !=========================================================================== ! The report below may be inaccurate. A more comprehensive ! resource usage report can be found at sha1/reports/report.html !=========================================================================== +--------------------------------------------------------------------+ ; Estimated Resource Usage Summary ; +----------------------------------------+---------------------------+ ; Resource + Usage ; +----------------------------------------+---------------------------+ ; Logic utilization ; 108% ; ; ALUTs ; 79% ; ; Dedicated logic registers ; 37% ; ; Memory blocks ; 42% ; ; DSP blocks ; 0% ; +----------------------------------------+---------------------------; aoc: First stage compilation completed successfully. Compiling for FPGA. This process may take a long time, please be patient. Error: Quartus Fitter has failed! Breaking execution... Error: Compiler Error, not able to generate hardware  

 

The end of quartus_sh_compile.log shows: 

Info: Command: quartus_cdb -t import_compile.tcl Info: Using INI file /home/gm78/intel/sha1_export_4_11_2018/device/sha1/quartus.ini Info: Checking for OpenCL SDK installation, environment should have INTELFPGAOCLSDKROOT defined Info: INTELFPGAOCLSDKROOT=/home/gm78/intelFPGA_pro/17.1/hld Info: Successfully completed BAK flow Info: To reduce compile time on future compiles, you can generate a BAK cache by adding the arguments '--bsp-flow regenerate_cache' to aoc to skip BAK Info: Retry strategy set to "retry-flat" Info: Initial preservation set to "final" Info (125061): Changed top-level design entity name to "top" Info (125061): Changed top-level design entity name to "kernel_system" Info (16677): Loading synthesized database Info (16734): Loading "synthesized" snapshot for partition "root_partition". Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:22 Info: Performing a fit attempt Error: Quartus Fitter has failed! Breaking execution...  

 

Not sure which log(s) are relevant to tracking down the problem. Please let me know and I can post the additional information. 

 

Many thanks.
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3 Replies
Altera_Forum
Honored Contributor I
32 Views

Logic utilization looks more than 100%. Usualy, when my logic utilization exceeds 90% I get the fit error. Try scalling down the device logic to 70% logic utilization and recompile it. This could also be because of less RAM in the host compile machine. Anyway you could first check the "quartus_sh_compile.log" to get first impressions about the compile error.

Altera_Forum
Honored Contributor I
32 Views

The area report, especially the logic utilization, is heavily overestimated on Arria 10 and hence, we cannot really make any conclusions based on that. Please attach the full "quartus_sh_compile.log" file.

Altera_Forum
Honored Contributor I
32 Views

After many many runs I determined the problem. It had to do with the amount of memory on the system ( 32 GiB ) and not enough swap space. I found this in the kernel log using: 

 

sudo cat /var/log/messages | grep -i quartus  

 

Increasing the swap space size and re-running the process proved successful. 

 

Thanks for the replies!
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