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Hello All,
I am trying to create a finite state machine which detects the input sequence 1011. I have written the code however I am getting about 21 errors. I am new to VHDL so what looks syntactically correct to me may be totally wrong. I would greatly appreciative if there is anybody who could take a look at my code and offer some advice as to what is creating the errors. My code is attached. Thanks
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The simplest way to detect a sequence is to use delay to remember past values(shift register):
in a clocked process use signal temp of 4 bits then
temp(3) <= data;
temp(2) <= temp(3);
temp(1) <= temp(2);
temp(0) <= temp(1);
if temp = "1011" then
sequence <= '1';
else
sequence <= '0';
end if; you can also just code
temp <= data & temp(3 downto 1);
you may reverse the shift direction depending on which way suits your sequence sense.
temp <= temp(2 downto 0) & data;
