Need help with RGMII RX violated hold slack

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Need help with RGMII RX violated hold slack

1,031 Views

Hi folks,

I need a little help with some timing issue. In a few words, I have a RGMII interface which I want to communicate with the Marvell PHY on the Cyclone V GT development board.

In my .sdc file, I have followed the AN477 example on connecting an fpga to an external phy device when the delay option is enabled (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an477.pdf), yet I get a large hold slack violation:

http://www.alteraforum.com/forum/attachment.php?attachmentid=13030&stc=1

I think my problem comes from the fact that the clock delay is quite high. How can I reduce it so that the "Data Required" ends before the next data arrival?

Regards,

Smith

18 KB

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.