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Altera_Forum
Honored Contributor I
2,063 Views

Need help with VHDL error here

Error (10476): VHDL error at scomp.vhd(64): type of identifier "AC_SHIFTED" does not agree with its usage as "std_logic_vector" type 

Error (10558): VHDL error at scomp.vhd(64): cannot associate formal port "RESULT" of mode "out" with an expression 

 

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL; 

USE IEEE.STD_LOGIC_ARITH.ALL; 

USE IEEE.STD_LOGIC_UNSIGNED.ALL; 

LIBRARY ALTERA_MF; 

USE ALTERA_MF.ALTERA_MF_COMPONENTS.ALL; 

LIBRARY LPM; 

USE LPM.LPM_COMPONENTS.ALL; 

ENTITY SCOMP IS PORT( 

CLOCK : IN STD_LOGIC; 

RESETN : IN STD_LOGIC; 

PC_OUT : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0); 

AC_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 

MDR_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 

MAR_OUT : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0); 

IO_WRITE : OUT STD_LOGIC; 

IO_CYCLE : OUT STD_LOGIC; 

IO_ADDR : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0); 

IO_DATA : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0) 

); 

END SCOMP; 

ARCHITECTURE a OF SCOMP IS 

TYPE STATE_TYPE IS ( 

RESET_PC, 

FETCH, 

DECODE, 

EX_LOAD, 

EX_STORE, 

EX_STORE2, 

EX_ADD, 

EX_SUB, 

EX_JNEG, 

EX_JPOS, 

EX_JZERO, 

EX_JUMP, 

EX_AND, 

EX_OR, 

EX_XOR, 

EX_ADDI, 

EX_SHIFT, 

AC_SHIFTED 

); 

 

 

SIGNAL STATE : STATE_TYPE; 

SIGNAL AC : STD_LOGIC_VECTOR(15 DOWNTO 0); 

SIGNAL IR : STD_LOGIC_VECTOR(15 DOWNTO 0); 

SIGNAL MDR : STD_LOGIC_VECTOR(15 DOWNTO 0); 

SIGNAL PC : STD_LOGIC_VECTOR(9 DOWNTO 0); 

SIGNAL MEM_ADDR : STD_LOGIC_VECTOR(9 DOWNTO 0); 

SIGNAL MW : STD_LOGIC; 

 

 

 

 

BEGIN 

SHIFTER: LPM_CLSHIFT -- Use LPM_CLSHIFT to shift AC 

GENERIC MAP( 

lpm_width => 16, 

lpm_widthdist => 4, 

lpm_shifttype => "LOGICAL" 

PORT MAP( 

data => AC, 

distance => IR(3 downto 0), 

direction => IR(4), 

result => AC_SHIFTED <----1st and 2nd error here 

); 

 

MEMORY : altsyncram -- Use altsyncram component for unified program and data memory 

GENERIC MAP ( 

intended_device_family => "Cyclone", 

width_a => 16, 

widthad_a => 10, 

numwords_a => 1024, 

operation_mode => "SINGLE_PORT", 

outdata_reg_a => "UNREGISTERED", 

indata_aclr_a => "NONE", 

wrcontrol_aclr_a => "NONE", 

address_aclr_a => "NONE", 

outdata_aclr_a => "NONE", 

init_file => "TEST_CODE.mif", 

lpm_hint => "ENABLE_RUNTIME_MOD=NO", 

lpm_type => "altsyncram" 

PORT MAP( 

wren_a => MW, 

clock0 => NOT(CLOCK), 

address_a => MEM_ADDR, 

data_a => AC, 

q_a => MDR 

); 

PC_OUT <= PC; 

AC_OUT <= AC; 

MDR_OUT <= MDR; 

MAR_OUT <= MEM_ADDR; 

IO_WRITE <= '0'; 

IO_CYCLE <= '0'; 

IO_ADDR <= IR(7 DOWNTO 0); 

WITH STATE SELECT 

MEM_ADDR <= PC WHEN FETCH, 

IR(9 DOWNTO 0) WHEN OTHERS; 

PROCESS (CLOCK, RESETN) 

BEGIN 

IF (RESETN = '0') THEN -- Active low, asynchronous reset 

STATE <= RESET_PC; 

ELSIF (RISING_EDGE(CLOCK)) THEN 

CASE STATE IS 

WHEN RESET_PC => 

MW <= '0'; -- Clear memory write flag 

PC <= "0000000000"; -- Reset PC to the beginning of memory, address 0x000 

AC <= x"0000"; -- Clear AC register 

STATE <= FETCH; 

WHEN FETCH => 

MW <= '0'; -- Clear memory write flag 

IR <= MDR; -- Latch instruction into the IR 

PC <= PC + 1; -- Increment PC to next instruction address 

STATE <= DECODE; 

WHEN DECODE => 

CASE IR(15 downto 10) IS 

WHEN "000000" => -- No Operation (NOP) 

STATE <= FETCH; 

WHEN "000001" => -- LOAD 

STATE <= EX_LOAD; 

WHEN "000010" => -- STORE 

STATE <= EX_STORE; 

WHEN "000011" => -- ADD 

STATE <= EX_ADD; 

WHEN "000100" => -- SUB 

STATE <= EX_SUB;  

WHEN "000101" => -- JUMP 

STATE <= EX_JUMP; 

WHEN "000110" => -- JNEG 

STATE <= EX_JNEG;  

WHEN "000111" => -- JPOS 

STATE <= EX_JPOS;  

WHEN "001000" => -- JZERO 

STATE <= EX_JZERO; 

WHEN "001001" => -- AND 

STATE <= EX_AND;  

WHEN "001010" => -- OR 

STATE <= EX_OR;  

WHEN "001011" => -- XOR 

STATE <= EX_XOR;  

WHEN "001101" => -- ADDI 

STATE <= EX_ADDI; 

WHEN "001100" => -- SHIFT 

STATE <= EX_SHIFT;  

WHEN OTHERS => 

STATE <= FETCH; -- Invalid opcodes default to NOP 

END CASE; 

WHEN EX_LOAD => 

AC <= MDR; -- Latch data from MDR (memory contents) to AC 

STATE <= FETCH; 

WHEN EX_STORE => 

MW <= '1'; -- Raise MW to write AC to MEM 

STATE <= EX_STORE2; 

WHEN EX_STORE2 => 

MW <= '0'; -- Drop MW to end write cycle 

STATE <= FETCH; 

WHEN EX_ADD => 

AC <= AC + MDR; 

STATE <= FETCH; 

WHEN EX_SUB => 

AC <= AC - MDR; 

STATE <= FETCH;  

WHEN EX_JUMP => 

PC <= IR(9 DOWNTO 0); 

STATE <= FETCH; 

WHEN EX_JNEG => 

IF AC(15) = '1' THEN 

PC <= IR(9 downto 0); 

END IF; 

STATE <= FETCH;  

WHEN EX_JPOS => 

IF AC(15) = '0' AND AC /= x"0000" THEN 

PC <= IR(9 downto 0); 

END IF; 

STATE <= FETCH;  

WHEN EX_JZERO => 

IF AC = x"0000" THEN 

PC <= IR(9 downto 0); 

END IF; 

STATE <= FETCH;  

WHEN EX_AND => 

AC <= AC AND MDR; 

STATE <= FETCH;  

WHEN EX_OR => 

AC <= AC OR MDR; 

STATE <= FETCH; 

WHEN EX_XOR => 

AC <= AC XOR MDR; 

STATE <= FETCH; 

WHEN EX_ADDI => 

IF IR(9)='0' THEN 

AC <= AC + ("000000"&IR(9 downto 0)); 

ELSE 

AC <= AC + ("111111"&IR(9 downto 0)); 

END IF; 

STATE <= FETCH; 

WHEN EX_SHIFT => 

AC <= AC_SHIFTED; 

STATE <= Fetch; 

WHEN OTHERS => 

STATE <= FETCH; -- If an invalid state is reached, return to FETCH 

END CASE; 

END IF; 

END PROCESS; 

END a;
0 Kudos
5 Replies
Altera_Forum
Honored Contributor I
355 Views

AC_SHIFTED is part of the state_type, and so has no specific value - the compiler will chose the value for you. If you want specific std_logic_vector values, you will need to specify them yourself. 

 

You also get the error because you're trying to assign a value to an out port (you can only connect an output to a signal, not a constant or an input).
Altera_Forum
Honored Contributor I
355 Views

TO_BE_DONE

Altera_Forum
Honored Contributor I
355 Views

main code has lots of components as below , above errors are associated with component calls in the main alu code. 

 

--LIBRARY USAGE 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.std_logic_signed.all; 

use ieee.numeric_std.all; 

 

--ENTITY OF 64 BIT ARITHMETIC LOGIC UNIT 

entity alu_64 is 

 

generic(K :natural:=64) ; 

port (input1 :in std_logic_vector(K-1 downto 0) ; 

input2 :in std_logic_vector(K-1 downto 0) ; 

alu_cont:in std_logic_vector(4 downto 0) ; 

clk :in std_logic ; 

reset :in std_logic ; 

alu_out :out std_logic_vector(K-1 downto 0) ; 

alu_rout:out std_logic_vector(K-1 downto 0) ; 

flag_reg:out std_logic_vector(4 downto 0)) ; 

 

end alu_64; 

 

--BEHAVIORAL DESIGN ARCHITECTURE OF 64 BIT ARITHMETIC LOGIC UNIT  

architecture behavioral of alu_64 is 

-----------------------------DECLERARION OF MUTIAL REQUIREMENTS--------------------------------- 

--Mutual signal declerations 

shared variable temp_alu_out :std_logic_vector(K-1 downto 0) ; 

shared variable temp_alu_rout:std_logic_vector(K downto 0) ;  

shared variable temp_flag_reg:std_logic_vector(4 downto 0) ; 

shared variable CF :std_logic ; 

shared variable OVF :std_logic ; 

shared variable ZF :std_logic ; 

shared variable PF :std_logic ; 

shared variable SF :std_logic ; 

 

--Mutual function decleration 

--Carry Flag function decleration  

function C_F(input : std_logic) return std_logic is 

begin 

if input = '1' then 

return '1'; 

end if; 

return '0'; 

end C_F; 

 

--Overflow Flag function decleration  

function OV_F(input : std_logic) return std_logic is 

begin 

if input = '1' then 

return '1'; 

end if; 

return '0'; 

end OV_F; 

 

--Zero Flag function decleration 

function Z_F(input : std_logic_vector) return std_logic is 

begin 

if input = x"00000000" then 

return '1'; 

end if; 

return '0'; 

end Z_F; 

 

--Parity Flag function decleration 

function P_F(input : std_logic_vector) return std_logic is 

variable counter:integer:= 0; 

begin 

for i in 0 to K-1 loop 

if(input(i) = '1') then 

counter := counter + 1; 

end if; 

end loop; 

if(counter mod 2 = 0) then 

return '1'; 

end if; 

return '0'; 

end P_F;  

 

--Sign Flag function decleration  

function S_F(input : std_logic) return std_logic is 

begin 

if(input = '1') then 

return '1'; 

end if; 

return '0'; 

end S_F;  

--------------------------------ARITHMETIC UNIT DECLERARIONS----------------------------------- 

--SIGNAL DECLERATIONS 

 

--Signal declerations for ADD_64 (64 bit unsigned adder) 

shared variable temp_add_out :std_logic_vector(K-1 downto 0); 

shared variable temp_cout :std_logic; 

 

--signal declerations for SADD_64 (64 bit signed adder) 

shared variable temp_sadd_out :std_logic_vector(K-1 downto 0); 

shared variable temp_scout :std_logic; 

 

--signal declerations for SUB_64 (64 bit unsigned subtracter) 

shared variable temp_sub_out :std_logic_vector(K-1 downto 0); 

shared variable temp_borrowout :std_logic; 

 

--signal declerations for SSUB_64 (64 bit signed subtracter) 

shared variable temp_ssub_out :std_logic_vector(K-1 downto 0); 

shared variable temp_sborrowout:std_logic; 

 

--signal declerations for MULT_64(64 bit signed and unsigned multiplier) 

shared variable temp_mult_out :std_logic_vector(2*K-65 downto 0); 

 

--signal declerations for DIV_64 (64 bit signed and unsigned divisor) 

shared variable temp_quotient :std_logic_vector(K-1 downto 0); 

shared variable temp_remainder :std_logic_vector(K downto 0); 

 

--signal declerations for MOD_64 (64 bit signed and unsigned modulator) 

shared variable temp_mod_out :std_logic_vector(K downto 0);
Altera_Forum
Honored Contributor I
355 Views

TO_BE_DONE

Altera_Forum
Honored Contributor I
355 Views

Port maps cannot be connected to shared variables - they can only connect to signals.

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