Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Need some help

Altera_Forum
Honored Contributor I
780 Views

Hey could someone help me and fix the problem , i can't find where i made the mistake , i'm new to this... 

 

library ieee; 

use ieee.std_logic_1164.all; 

 

 

 

 

 

entity sck is 

port ( 

 

i_bit0 : in std_logic_vector(1 downto 0); 

o_bit1 : in std_logic_vector(1 downto 0); 

o_bit2 : out std_logic_vector(5 downto 0)); 

); 

 

 

end sck; 

 

architecture behavioral of sck is 

signal A: std_logic_vector(5 downto 0); 

begin 

A<= o_bit1 and o_bit2; 

process (A) 

begin 

case i_bit0  

when "00" => A <="011100"; 

when "01" => A <="101010"; 

when "10" => A <="110011"; 

when "11" => A <="111111"; 

when others => null; 

end case; 

end process; 

 

end behavioral;
0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
66 Views

What error(s) are you getting? 

 

You have an extra ) and ; for the o_bit2 port.
Reply