Nested SystemVerilog/Verilog Include Files

[david_]

Hi,

I am importing a SystemVerilog project into a Cyclone 10GX using Quartus Pro 21.2, but unfortunately I am getting some issues.

This project has include files to define various parameters. One of the include files includes another include file at the top. This is where I think I am getting an issue.

To me it looks like it may be evaluating the include file that has another include file in it before evaluating the include file that it relies on. I have made a small dummy project that illustrates the issue and get the following error:

Error(13406): Verilog HDL error at parameters.vh(1): object "param_t" is not declared 

Is there a way to control the order in which include files are evaluated? Currently I add the include files using the following command in my tcl script:

set_global_assignment -name SEARCH_PATH "../../include"

I have attached the small project. To create the project it I go to /nested_include_test/cyclone10_gx then run

quartus_sh -t nested_include_test.tcl

in Linux. The project file will then be in the work folder below.

Thanks

David

[sstrell]

Shouldn't the paths be "../include" etc., not "../../include"?  You're going up two levels instead of 1.

[david_]

Hi, no the synthesis script creates a work folder which it cd's into to put all the generated project files. From there it is 2 levels up.

[Nurina]

Hi David,

Did the above reply help?

Nurina

[david_]

Hi, no, not yet. Thanks

[Nurina]

Hi,

This KDB teaches how you can use parameters in header files: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07231998_9862.html

Also make sure you set the correct Verilog version, typedef is SystemVerilog not Verilog.

Regards,

Nurina

[david_]

Hi,

Unfortunately the KDB did not help me. I changed the build script to include

set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2012

but that didn't remove the error.

I have attached the project as it stands if it would be possible for you to have a look? It has not really changed from the first post, apart from having the SystemVerilog flag. It is run in the same way.

Thanks

David

[david_]

Maybe it could be something to do with this warning?

Warning(16847): Verilog HDL warning at parameters.vh(8): concatenation member label not yet supported; label ignored 

[Nurina · Accepted solution]

Hi,

I think the problem is the fact that you declared a typedef in a header file. Because they're usually declared in a verilog HDL file before the module declaration, but I don't think that's what you want to do.

Header files are problematic in general, which is why SystemVerilog introduced us to packages: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6469140

You should use packages instead of `include. You can populate packages with parameters too.

Regards,

Nurina

[david_]

Hi Nurina, ok thanks Il convert it to a package. It is a Xilinx project that I am importing and works there.

Regards

David

[Nurina]

Hi David,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,
Nurina

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!